Although Wiki warns that MEMW is required between GPIO register writes, it is occasionally missing. So, e.g., in brzo_i2c.c lines 332-333 the actual order of SDA LOW and SCL HIGH may depend on how the CPU manages the cache. Also in some cases MEMW is missing between a register write and a timing loop, e.g. line 309. If the CPU delays writing to memory, the SCL pulse would end up shorter by the amount of this delay, no?
Although Wiki warns that MEMW is required between GPIO register writes, it is occasionally missing. So, e.g., in brzo_i2c.c lines 332-333 the actual order of SDA LOW and SCL HIGH may depend on how the CPU manages the cache. Also in some cases MEMW is missing between a register write and a timing loop, e.g. line 309. If the CPU delays writing to memory, the SCL pulse would end up shorter by the amount of this delay, no?