It seems (correct me if I'm wrong) that BRZO uses the following clock stretch logic:
Release SCL (i.e., set SCL HIGH).
Wait time T equal to one half clock cycle.
Read SCL.
A. If SCL is still LOW, assume the slave is stretching clock. Wait for SCL to go HIGH, then let it stay HIGH for half-cycle time T, then bring it LOW to read/write the next bit.
B. If SCL is HIGH, assume the slave is not stretching clock. Bring SCL LOW immediately to read/write the next bit.
The consequence is that if the slave stretches clock by an amount less than T, BRZO will not notice, will bring SCL LOW, and the SCL pulse could end up being very short. But I'm puzzled because BRZO seems to be deliberately coded in this way. Why? Am I missing something?
It seems (correct me if I'm wrong) that BRZO uses the following clock stretch logic:
The consequence is that if the slave stretches clock by an amount less than T, BRZO will not notice, will bring SCL LOW, and the SCL pulse could end up being very short. But I'm puzzled because BRZO seems to be deliberately coded in this way. Why? Am I missing something?