System block diagram with BRAMs and ZynQ processor.

patryk-oleniuk / cnn_hw_accelerator

FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ

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System block diagram with BRAMs and ZynQ processor. #3

Open tansyab1 opened 5 years ago

tansyab1 commented 5 years ago

Can you share me more detail about the connection between BRAMs and ZynQ processor? the System block diagram with BRAMs and ZynQ processor figure in your report is so blur ? thanks so much

patryk-oleniuk commented 5 years ago

I just uploaded the whole Vivado project in this repo, you should be able to just open it and compile nicely :)

tansyab1 commented 5 years ago

thank you very much but I dont see any change in this repo.

patryk-oleniuk commented 5 years ago

Sorry, it took a while for github to process the file. It should be here now in sw/Vivado_project_files