Linux tests

[paulfloyd]

On cfarm117 AMD Opteron 1100 (ARMv8-A) Debian 9.13 stretch 4.9.0-18-arm64

Clean git HEAD

== 695 tests, 13 stderr failures, 0 stdout failures, 0 stderrB failures, 1 stdoutB failure, 9 post failures ==
gdbserver_tests/hgtls                    (stdoutB)
memcheck/tests/dw4                       (stderr)
memcheck/tests/linux/sys-preadv2_pwritev2 (stderr)
memcheck/tests/supp_unknown              (stderr)
memcheck/tests/varinfo2                  (stderr)
memcheck/tests/varinfo4                  (stderr)
memcheck/tests/varinfo5                  (stderr)
memcheck/tests/varinfo6                  (stderr)
memcheck/tests/varinforestrict           (stderr)
helgrind/tests/hg05_race2                (stderr)
helgrind/tests/tc20_verifywrap           (stderr)
drd/tests/bar_bad                        (stderr)
drd/tests/tc04_free_lock                 (stderr)
drd/tests/tc09_bad_unlock                (stderr)

This repo

== 695 tests, 13 stderr failures, 1 stdout failure, 0 stderrB failures, 1 stdoutB failure, 9 post failures ==
gdbserver_tests/hgtls                    (stdoutB)
memcheck/tests/dw4                       (stderr)
memcheck/tests/leak-segv-jmp             (stderr)
memcheck/tests/linux/sys-preadv2_pwritev2 (stderr)
memcheck/tests/supp_unknown              (stderr)
memcheck/tests/varinfo2                  (stderr)
memcheck/tests/varinfo4                  (stderr)
memcheck/tests/varinfo5                  (stderr)
memcheck/tests/varinfo6                  (stderr)
memcheck/tests/varinforestrict           (stderr)
helgrind/tests/hg05_race2                (stderr)
helgrind/tests/tc20_verifywrap           (stderr)
drd/tests/tc04_free_lock                 (stderr)
drd/tests/tc09_bad_unlock                (stderr)
none/tests/arm64/memory                  (stdout)

Extra fails: none/tests/arm64/memory memcheck/tests/leak-segv-jmp

Extra passes drd/tests/bar_bad

[paulfloyd]

For 'memory' it's these 3

MEM_TEST("xyzzy10: ldr s17, xyzzy10 - 8", 0, 0)
MEM_TEST("xyzzy11: ldr d17, xyzzy11 + 8", 0, 0)
MEM_TEST("xyzzy12: ldr q17, xyzzy12 + 4", 0, 0)

If I install gcc and compile the testcase with it then I get the old result.

"ldr s17" I think that means a 32 bit load

[paulfloyd]

I think that I see.

We have, from the macro

"ldr x5, [%0, #80] ; " \ "ldr x6, [%0, #88] ; " \ INSN " ; ... : : "r"(&block[0])

and the macro instantiation

MEM_TEST("xyzzy10: ldr s17, xyzzy10 - 8", 0, 0)

If I understand right, this is reading 32bits from the insruction text 8 bytes before the ldr. That should be the ldr x5 instruction.

The ldr instruction is "put into x8 the contents pointed to by the register used for variable block with an offset of 0x80".

The problem is that the compiler can use different registers for block.

GCC: objdump 452e34: f9402805 ldr x5, [x0, #0x50]

(gdb) p /x (unsigned int)$s17 $1 = 0xf9402805

clang: objdump 250a38: f9402905 ldr x5, [x8, #0x50]

(gdb) p /x (unsigned int)$s17 $2 = 0xf940290

[paulfloyd]

mmit 2c749b8613940c3ee7624aa11048cf529d227d01 (HEAD -> freebsdarm64_valgrind, github/freebsdarm64_valgrind) Author: Paul Floyd pjfloyd@wanadoo.fr Date: Sun Mar 10 14:05:05 2024 +0100

Add an expected for none arm64 memory

There are a few small compiler dependencies