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paulscherrerinstitute / psi_multi_stream_daq

Data acquisition of multiple AXI-S streams to a memory connected via AXI-MM (e.g. DDR memory) written in VHDL
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Timeout causes core hang #3

Open hjaec opened 3 years ago

hjaec commented 3 years ago

When a timeout occurs on a stream with no samples in the input buffer, a zero size command is issued. This hangs the axi master in the memory interface.

(WrWconvFsm: WrWordsDone initialized with 1, WrDataWordsWc is 0, thus state Transfer_s with transition condition WrWordsDone == WrDataWordsWc is never left)