connect_bd_net invocations in block_design.tcl fail on Vivado 2022.1

[polprog]

I am using the block_design.tcl files from this repository to create a block design for the Red Pitaya. On Vivado 2022.1 the command connect_bd_net fails:

connect_bd_net [get_bd_ports SPI0_MISO_I] [get_bd_pins ps_0/SPI0_MISO_I]
WARNING: [BD 5-235] No pins matched 'get_bd_pins ps_0/SPI0_MISO_I'
ERROR: [BD 41-701] connect_bd_net requires at least two pins/ports, or one pin/port and a net

This is because the Processing System block has SPI0 disabled by default, therefore there are no SPI0_* pins available.

You need to run the command

set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] [get_bd_cells ps_0]

in order for the block design tcl to go through.

[pavel-demin]

What project from this repository are you trying to build?

The only project that has the connect_bd_net [get_bd_ports SPI0_MISO_I] [get_bd_pins ps_0/SPI0_MISO_I] command seems to be red_pitaya_0_92. This particular project is very likely not working because I stopped using and maintaining it 8 years ago. I should probably delete it from this repository.

If some projects do not work when built with Vivado 2022.1, try the develop branch. It is better compatible with Vivado 2022.1.