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pavel-demin / red-pitaya-notes

Notes on the Red Pitaya Open Source Instrument
http://pavel-demin.github.io/red-pitaya-notes/
MIT License
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Fix AXIS DAC IP timing for DAC latching #1118

Closed traavnik closed 11 months ago

traavnik commented 11 months ago

Hi Pavel, While using your wonderful project as a base for my custom development, I encountered a problem with the AXIS DAC IP. I couldn't get it to latch a single data transfer (1 clock tvalid). Turns out dac_rst had to be delayed to let the IP clock out the data and then instruct the AD9767 DAC to latch it (see attached image from the datasheet). Without delay, the DAC would latch the 'b0 frame which is clocked out whenever tvalid is not present.

image

The DAC is perfectly happy keeping the value latched indefinitely.

I've tested the IP with a sparse stream on a RedPitaya board. I expect no significant change to continuous streams apart from skipping erroneous 'b0 sample "injection" at the start of the stream.

Please consider checking this PR. Thanks!

pavel-demin commented 11 months ago

Thank you for finding this problem. I have added the fix with this commit with a slightly different coding style.