Memory specification in the block design

[marcomeixner]

Hey Pavel,

I am trying to figure out how the data is sent from the FPGA to the c program.

If I am not mistaken the fifo to pick up the data is specified in this line in the c program: fifo = mmap(NULL, 16*sysconf(_SC_PAGESIZE), PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0x42000000);

I have been looking in the tcl files and the block design for this memory adress, but no success so far.

So I am wondering how the FPGA knows which memory adress to put the data and which IP block takes care of that..

Thank you so much and best wishes, Marco

[pavel-demin]

Hi Marco,

The address 0x42000000 of the FIFO buffer is the sum of the base address of interface M_AXI_GP0 (0x40000000) and the base address of interface 0 (0x02000000) of the AXI4 hub.

The address ranges of the M_AXI_GP0 and M_AXI_GP1 interfaces are shown in table 4-1 of the Zynq-7000 TRM.

The AXI4 hub uses bits 24 to 27 of the address to select one of its ports. The complete table of addresses can be found at this link.

[marcomeixner]

Thank you!