TCL script fails in adc_recorder project

[mrengineer]

Description of the setup:

• Device: TRX-DUO (but it does not matter on this step)
• SD card image: 20240204
• Application: adc_recorder
• Other relevant information:

Description of the problem:

I am trying to build FPGA bitstream to continue with it. But TCL script fails.

Steps to reproduce the problem:

1. Download red-pitaya-notes/projects/adc_recorder/block_design.tcl

2. Run Vivado. Select Tools -> Run TCL script...

3. In TCL console I see

source /home/user/red-pitaya-notes/projects/adc_recorder/block_design.tcl
# cell xilinx.com:ip:clk_wiz pll_0 {
#   PRIMITIVE PLL
#   PRIM_IN_FREQ.VALUE_SRC USER
#   PRIM_IN_FREQ 125.0
#   PRIM_SOURCE Differential_clock_capable_pin
#   CLKOUT1_USED true
#   CLKOUT1_REQUESTED_OUT_FREQ 125.0
#   USE_RESET false
# } {
#   clk_in1_p adc_clk_p_i
#   clk_in1_n adc_clk_n_i
# }
invalid command name "cell"
    while executing
"cell xilinx.com:ip:clk_wiz pll_0 {
  PRIMITIVE PLL
  PRIM_IN_FREQ.VALUE_SRC USER
  PRIM_IN_FREQ 125.0
  PRIM_SOURCE Differential_clock_capable_pin
  C..."
    (file "/home/user/red-pitaya-notes/projects/adc_recorder/block_design.tcl" line 2)

I have tried with Vivado 2019.2 and 2023.2 with same result.

Please, help with it Thank you!

[pavel-demin]

My scripts were never meant to work the way you use them, so it is normal that they do not work that way.

Please take a look at my notes at the following link:

http://pavel-demin.github.io/red-pitaya-notes/

These notes explain how to use my scripts and what version of Vivado to install.

To build the adc_recorder project, the following commands should be used:

source /opt/Xilinx/Vitis/2023.1/settings64.sh

git clone https://github.com/pavel-demin/red-pitaya-notes
cd red-pitaya-notes

make NAME=adc_recorder bit