AXI Stream to Memory mapped

[jeanminet]

Hello Pavel,

Thanks a lot for your very helpful work ! In your sdr_transceiver project, you use a Xilinx FIFO generator core in combination with two custom cores (axi_axis_reader and axi_axis_fifo) in order to have a memory mapped access to the data stream:

It looks like this functionality could be implemented with the Xilinx AXI-Stream FIFO core:

I was wondering if I missed something. Does your combination provide better throughput ?

Best, Jean

[pavel-demin]

Hello Jean,

Does your combination provide better throughput ?

Throughput - I don't know, maybe. Features - yes.

I've once simplified the AXI4-Lite interface in all my AXI4-Lite cores with the following commit: https://github.com/pavel-demin/red-pitaya-notes/commit/663e313b6ccf3cb0a866e85cce2f7de34704d633.

I've tried several AXI and AXIS FIFO cores provided by Xilinx but without much success. They behaved strangely, had some features that I didn't need, missed some features that I needed.

My projects often require the following features:

• mixed ports widths,
• s_axis_tready and m_axis_tvalid always high,
• m_axis_tdata low if FIFO is empty.

Both axi_axis_reader and axis_fifo are very simple and do exactly what I need.

Best regards,

Pavel

[jeanminet]

That makes sense. I didn't realize the axis_fifo core was so simple !