search

pavel-demin / red-pitaya-notes

Notes on the Red Pitaya Open Source Instrument
http://pavel-demin.github.io/red-pitaya-notes/
MIT License
337 stars 209 forks source link

VHDL equivalent cores #384

Closed kkomnisys closed 7 years ago

kkomnisys commented 7 years ago

Hi!

Is it possible to get VHDL equivalents of the Verilog cores in this repository and a setting in the Makefile/project.tcl to set preferred HDL language?

Keep up the good work

pavel-demin commented 7 years ago

If I'm not mistaken, Vivado supports mixing VHDL and Verilog in a single project.

It's not impossible that it'd be enough to just add *.vhdl to core.tcl and project.tcl at the following lines: https://github.com/pavel-demin/red-pitaya-notes/blob/master/scripts/core.tcl#L14 https://github.com/pavel-demin/red-pitaya-notes/blob/master/scripts/project.tcl#L80

Is it possible to get VHDL equivalents of the Verilog cores in this repository

I'm not sure if I understand what do you mean by VHDL equivalents. Normally, IP cores written in VHDL and Verilog can be mixed in a single Vivado project.

If you require the code of the IP cores to be translated from Verilog to VHDL, then it can be done manually or with an automatic Verilog to VHDL translator.