Closed madmaxII closed 7 years ago
Setting the CIC decimation rate isn't enough. You'll also need to change the FIR sample rate. But the problem is that after these changes this configuration won't fit into the Red Pitaya FPGA. I'd suggest to try the following changes:
Hello Pavel,
is it possible to configure the sdr transceiver wide to 5Mhz bandwidth?
I tried to set the CIC with R = 10 (using the script to generate fir coefficients), but it does not work well.
Thanks in advance.