Stuck in the tutorial - can't generate bitstream

[RadimPav]

I have followed the tutorial : https://red-pitaya-fpga-examples.readthedocs.io/en/latest/_downloads/StartprogrammingFPGAusingRedPitayaboard.pdf

And the result of my compilation is following (bit-stream is not generated) :/

INFO: [Synth 8-256] done synthesizing module 'axi4_slave' (6#1) [/home/redpitaya/GitHub_RedPitaya/RedPitaya/fpga/rtl/axi4_slave.sv:49]
ERROR: [Synth 8-439] module 'system' not found [/home/redpitaya/GitHub_RedPitaya/RedPitaya/fpga/prj/classic/rtl/red_pitaya_ps.sv:92]
ERROR: [Synth 8-285] failed synthesizing module 'red_pitaya_ps' [/home/redpitaya/GitHub_RedPitaya/RedPitaya/fpga/prj/classic/rtl/red_pitaya_ps.sv:28]
ERROR: [Synth 8-285] failed synthesizing module 'red_pitaya_top' [/home/redpitaya/GitHub_RedPitaya/RedPitaya/fpga/prj/classic/rtl/red_pitaya_top.sv:52]

Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1107.039 ; gain = 169.555 ; free physical = 3889 ; free virtual = 6968

RTL Elaboration failed
INFO: [Common 17-83] Releasing license: Synthesis
106 Infos, 0 Warnings, 0 Critical Warnings and 4 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
INFO: [Common 17-206] Exiting Vivado at Fri Sep 21 09:55:33 2018...
Makefile:40: recipe for target 'prj/classic/out/red_pitaya.bit' failed
make: *** [prj/classic/out/red_pitaya.bit] Error 1

Does anybody know how to advance and how to make him see the module 'system'?

[pavel-demin]

Sorry, I can't help you with this problem. I'm not using the code from the RedPitaya repository.