Question: axis_red_pitaya_dac data rate

[Apollo3zehn]

Hi Pavel,

I have a question about your axis_red_pitaya_dac IP. When I simulate this IP in Vivado, I can see that the update rate of dac_dat is equal to the aclk input:

But according to the DAC datasheet, it should update with twice the clock in interleaved mode. So the data should update at the same rate as the ddr_clk (IQCLK) input.

So I would say this line of code should be changed to .C(ddr_clk), to ensure the correct data rate.

What dou think? Did I overlook somethink?

Thanks Vincent

[pavel-demin]

Thanks for checking the axis_red_pitaya_dac module.

What dou think? Did I overlook somethink?

Your simulated timing diagram shows the following:

• the DAC data is updated on the falling edge of the dac_clk clock,
• the rising edge of the dac_clk happens when the DAC data is stable.

So, your simulated timing diagram confirms that the axis_red_pitaya_dac module works correctly.

The internal DAC data registers (int_dat_a_reg and int_dat_b_reg) are connected to the output DDR register. The DDR register updates its output (dac_dat) on both the rising and falling edges of the aclk clock. So, dac_dat is update twice per the aclk clock period.

[Apollo3zehn]

You are right, I misinterpreted my simulation. Thanks for clarification :)