Allow for clock 1 and clock 2 to both run, but at the same frequency and different phase settings

[wa2mze]

It should be possible to run both clock 1 and clock 2 at the same time if they are set to the same frequency. Why do this? So they can be run 90 degrees apart in phase to drive an I/Q demodulator. It seems that just loading the phase registers with the correct constant and having the PLL run at an even multiple of the desired frequency should do this according the the eitherkit library readme file.

[wa2mze]

I'm experimenting with code to limit the divisor to 126, and as an even number. A minimum PLL frequency of 400 mhz will allow for I/Q outputs as low as 3mhz (with a 25mhz crystal). (technically out of spec, but proven to work). I will then provide a set_frequency method that will program clk1 and clk2 to run with the same PLL, at the same frequency. The phase_offset register for one of these channels will be set to the divisor value (4-126) to set that clk channel to a 90 degree phase offset. Another method will allow changing the offset from 90 to 270 degrees (invert phase output) for use in sideband selection with I/Q (de)modulators. The enable method will now allow both clks 1 and 2 to be enabled, or just one of them. If only one channel is enabled, it will (must) be the Inphase output and not the Quadature output. The PLL will ONLY be reset during the set_frequency method if the divisor has changed since the last set_frequency request.

[motorist828]

Hello, I have a similar suggestion. For my project, the second output needs an inverted signal with the same frequency, can this be done somehow?

[wa2mze]

If the phase of the second output is set to 180 degrees instead of 90, that would be an inverted output. I'm not exactly sure how to set the phase register for this, but suspect that it should be a specific multiple of the divisor.

[sbridger]

Quadrature outputs are also important for me.

As an aside, I would also note that having a third output sometimes is useful for built-in self-test. It has no requirement to be click free, or even have fine frequency resolution, it just allows use as a BIST signal generator.

[koendv]

Inverting a clock (e.g. for differential output) is done in CLK0_INV and CLK1_INV, register 16 and 17, bit 4.

[koendv]

I add C source that configures CLK1 to be the inverse of CLK0. Uses include file from milldrum to keep code legible.

si5351mcu_diff.txt

This code sets CLK1_INV to set CLK1 to the inverse of CLK0. You can get a 90 degree phase shift in a similar way. [Edit: tweaked source to show clk0 needs to be initialized first.]