Currently, the TX direction of the emulator will never stall, even if the RX FIFO of the receiver is full. In that case, data will be buffered within 0MQ until the data can be pushed to the FIFO, so no data will get lost. However, this can lead to drastically different behavior, where executions working in emulation will deadlock in hardware.
To achieve a better quality of emulation results, (optional) flow control similar to the one used in hardware should be implemented in the emulator to prevent buffering of data outside the FIFOs.
Currently, the TX direction of the emulator will never stall, even if the RX FIFO of the receiver is full. In that case, data will be buffered within 0MQ until the data can be pushed to the FIFO, so no data will get lost. However, this can lead to drastically different behavior, where executions working in emulation will deadlock in hardware. To achieve a better quality of emulation results, (optional) flow control similar to the one used in hardware should be implemented in the emulator to prevent buffering of data outside the FIFOs.