Explicit latency annotations on Values?

[VonTum]

In the example:

// Recursive Tree Add module recurses smaller copies of itself. 
module TreeAdder #(int WIDTH) {
    interface TreeAdder : int[WIDTH] values'0 -> int total

    if WIDTH == 0 {
        // Have to explicitly give zero a latency count. 
        // Otherwise total's latency can't be determined. 
        int zero'0 = 0
        total = zero
    } else if WIDTH == 1 {
        total = values[0]
    } else {
        gen int L_SZ = WIDTH / 2
        gen int R_SZ = WIDTH - L_SZ

        int[L_SZ] left_part, int[R_SZ] right_part = SplitAt(values)

        int left_total = TreeAdder(left_part)
        int right_total = TreeAdder(right_part)

        // Can add pipelining registers here too. 
        // Latency Counting will figure it out.
        reg total = left_total + right_total
    }
}

We use int zero'0 = 0 because otherwise the LC system can't figure out the absolute latency for total

Perhaps we could add a way to annotate the constant directly? Like total = 0'0