Closed SiarheiVolkau closed 3 years ago
Sorry, I didn't see this bug report.
I don't know what you are talking about though. Current ratios are already /3. If you set HDIV/PDIV/MDIV to 2, then the ratios are /2.
Yep, you are right, I miss the n2FR
array usage, sorry.
BTW my handheld is able to work on the /2 rates, but it is out of specifications and not very stable.
So no actions needed, thank you.
@SiarheiVolkau One thing you can try is to set the PLL to 2x its nominal frequency (e.g. 360 MHz -> 720 MHz) and use dividers 2/6/6/6/6. Strangely on lepus boards (JZ4760) that makes a noticeable difference. I didn't test on the JZ4725B.
The SDRAM clock ratio seems not optimal for JZ4725B based devices (RS-90, RG99). Current ratio is /4 which leads to 90MHz effective clock speed on default 360MHz CPU clock.
It's possible to set ratio to /3 thus get 120MHz effective SDRAM frequency which lead to better overall performance. Has tested on similar device Ritmix RZX-27 (JZ4725B and Etrontech EM63A165TS-6G SDRAM chip) and observed performance is 10-20% better on the same CPU speed.
Unfortunately the maximal CPU overclock is limited by 420MHz but performance seems higher than on 456MHz CPU clock with /4 ratio of SDRAM. How to set ratio /3 - redefine
HDIV
andPDIV
andMDIV
to2
in the desired board file.