Closed satar1980 closed 1 year ago
This is basic C code, but here we go.
The first line creates a macro that can be used as a function called FPGA_CTRL_INIT and loads a memory address with the content of itself anded with 0xFFFFF000 and ored with 0x00000111.
It is the same as having a function like:
inline void FPGA_CTRL_INIT(void) { FPGA_CTRL_CFG_REG = (FPGA_CTRL_CFG_REG & 0xFFFFF000) | 0x00000111; }
What this code does in the context of this system is that it sets some of the IO pins used for the connection with the FPGA to be outputs.
The rest of the macros do similar things, but make use of the IO pins data register, manipulating the status of the output pins.
i mean, for this line example:
0xFFFFF9FF -> this value came from where and what the meaning. like that.
can you give me reference or manual book sir. i was search on google but not found literature can help. i just have manual F1C100s , but not help me so much.
Several manuals for this project can be found here https://github.com/pecostm32/FNIRSI-1013D-1014D-Hack/tree/main/Manuals
The meaning of the 0xFFFFF9FF becomes clear when you convert it to binary. Since it is anding with this value, the one bits are left as is, but the zero ones are cleared after the and operation. So bits 9 and 10 (counting from the right and starting with 0) are made zero. These are the lines for controlling the communication with the FPGA. After the or operation bit 9 is set to one.
Bits 9 and 10 are the lines that set the mode. Either data or a command is read or written from or to the FPGA. 2 bits means 4 combinations.
Bit 8 is the clock signal.
You can find more information about it on EEVBlog. Use the links provided in the top readme file.
In the F1C100s manual you can find the description for the general purpose io ports used.
b1111100111111111 | b0000001000000000 oh i see,
one more sir, i add rotary encoder interrupt, i use pin P9, P10, on my board, rotary encoder run normal, and when i try to send byte 0xFF ( fpga_write_byte(0xFF) ), pin PE0 - 7 still LOW. but if i delete rotary encoder interrupt function, pin PE0 - 7 to be normal the result is HIGH. my question is why ? can you help find where is the fault sir
this is the code i added:
volatile int Pulse; int lastStateCLK;
uint8_t rot_get_state() { return (uint8_t)((gpio_pin_get(GPIOE, 9) << 1) | (gpio_pin_get(GPIOE, 10))); }
void flag() { uint8_t s = rot_get_state();
if(lastStateCLK==1 && s==0) return; if(lastStateCLK==2 && s==3) return;
// add 1 to count for CW if (s==1 || s==2) { Pulse=-1 ; }else if (s==0 || s==3) { Pulse=1 ;
}
printf("[stete: %d ]",s);
lastStateCLK = s;
}
void encoder_interrupt_init(void) { FPGA_CTRL_CFG_REG = (FPGA_CTRL_CFG_REG & 0xFFFFF00F) | 0x00000660;
EINT_PE_CFG_REG1 = (EINT_PE_CFG_REG1 & 0xFFFFF00F) | 0x00000440;
*EINT_PE_ENB_REG |= 1 << 9 ;
*EINT_PE_ENB_REG |= 1 << 10 ;
gpio_ext_init(GPIOE_, GPIO_PIN_9, flag);
f1c100s_intc_set_isr(F1C100S_IRQ_GPIOE, do_gpio_irq,0);
f1c100s_intc_set_priority(F1C100S_IRQ_GPIOE,1);
f1c100s_intc_unmask_irq(F1C100S_IRQ_GPIOE);
f1c100s_intc_enable_irq(F1C100S_IRQ_GPIOE);
}
I'm no clairvoyant, so can't help with this.
I think you are adding hardware where it can't be added and using functions that are not part of the original code.
The FPGA bus is dedicated to communicating with the FPGA and connecting a rotary encoder to it can damage both the MCU and the FPGA.
yah, i am added some function from another source (https://github.com/nminaylov/F1C100s_projects), maybe there is an mistake for my board. i don't have fpga yet, only have f1c200s board and stm32. so I try to simulate with stm32 for adc input. thank you sir I really appreciate your help.
Best to register on EEVBlogand ask these questions in the microcontroller section. (https://www.eevblog.com/forum/microcontrollers/) Be very specific and add pictures plus schematics of your setup. You can catch a wider audience of experts there.
This issue has nothing to do with the FNIRSI 1013D, so to me this issue is closed.
i need help. can anyone explain line by line this code :
//Initialize the control lines for communication with the FPGA (PE8:10 output)
define FPGA_CTRL_INIT() FPGA_CTRL_CFG_REG = (FPGA_CTRL_CFG_REG & 0xFFFFF000) | 0x00000111
//Initialize the clock line to high
define FPGA_CLK_INIT() (*FPGA_DATA_REG |= 0x00000100)
//Set the different target options for communication with the FPGA
define FPGA_CMD_WRITE() (FPGA_DATA_REG = (FPGA_DATA_REG & 0xFFFFF9FF) | 0x00000600)
define FPGA_CMD_READ() (FPGA_DATA_REG = (FPGA_DATA_REG & 0xFFFFF9FF) | 0x00000400)
define FPGA_DATA_WRITE() (FPGA_DATA_REG = (FPGA_DATA_REG & 0xFFFFF9FF) | 0x00000200)
define FPGA_DATA_READ() (FPGA_DATA_REG = (FPGA_DATA_REG & 0xFFFFF9FF) | 0x00000000)
//Clock control
define FPGA_PULSE_CLK() (FPGA_DATA_REG &= 0xFFFFFEFF);(FPGA_DATA_REG |= 0x00000100)
//Put data on or get data from the FPGA databus
define FPGA_SET_DATA(x) (FPGA_DATA_REG = (FPGA_DATA_REG & 0xFFFFFF00) | (x & 0x000000FF))
define FPGA_GET_DATA() (*FPGA_DATA_REG & 0x000000FF)