pellepl / spiffs

Wear-leveled SPI flash file system for embedded devices
MIT License
1.52k stars 402 forks source link

Cache size calculations are inconsistent? #274

Open jcwren opened 3 years ago

jcwren commented 3 years ago

I was recently reevaluating a project for much cache to use, and I'm finding conflicting ways of allocating the cache buffer, as far as how much space is needed.

In src/test/test_spiffs.c, it's done this way (which is the way SPIFFS_buffer_bytes_for_cache() defines it in `src/spiffs_hydrogen.c):

  _cache_sz = sizeof(spiffs_cache) + cache_pages * (sizeof(spiffs_cache_page) + log_page_size);

In the integration Wiki page, it's done this way:

  static u8_t spiffs_cache_buf[(LOG_PAGE_SIZE+32)*4];

(We also see a magic number of 32 in that. Why 32? sizeof (spiffs_cache_page) is 20, at least on the Cortex M4 implementations)

Yet in src/spiffs_hydrogen.c, there's a hard clipping of 32 * the logical page size in SPIFFS_mount():

  fs->cache_size = (cache_size > (SPIFFS_CFG_LOG_PAGE_SZ(fs)*32)) ? SPIFFS_CFG_LOG_PAGE_SZ(fs)*32 : cache_size;

Using SPIFFS_buffer_bytes_for_cache() function for 32 pages, I get 8852 bytes for the buffer size. Yet in the code above, it's clipping it to 8192 bytes. SPIFFS_CFG_LOG_PAGE_SZ is defined as 256 in my implementation.

I spent a little time trying to follow the bouncing ball for how it "formats" the cache buffer, but I got lost. It seems that it's either not really possible to have a true 32 pages of cache (subsequent calculations wouldn't see enough space available), or SPIFFS_buffer_bytes_for_cache() isn't updated to reflect how much memory is actually needed for the cache.