The RAM version also needs to initialize the cache

As discussed earlier in https://github.com/pepe2k/u-boot_mod/issues/48#issuecomment-493643150

in cpu/mips/start.S, the following code blocks should also be executed in RAM version:

rel_start:

//#ifndef CONFIG_SKIP_LOWLEVEL_INIT
    /* Initialize caches... */
    la   t9, simple_mips_cache_reset
    jalr t9
    nop

    /* ... and enable them */
#if (SOC_TYPE & QCA_AR934X_SOC)
    li   t7,   KSEG1ADDR(QCA_RST_REVISION_ID_REG)
    lw   t7,   0(t7)
    andi t9,   t7, 0xf
    bne  zero, t9, 1f
    nop

    li t0, CONF_CM_UNCACHED
    j  2f
    nop
#endif

1:
    li   t0, CONF_CM_CACHABLE_NONCOHERENT
2:
    mtc0 t0, CP0_CONFIG

#if (SOC_TYPE & QCA_AR933X_SOC) || \
    (SOC_TYPE & QCA_AR934X_SOC)
    la   t9, mips_cache_lock_24k
    jalr t9
    nop
#endif

//#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */

pepe2k / u-boot_mod

The RAM version also needs to initialize the cache #227