Vivado 2017.2 issues

[mopplayer]

Hi, peteasa. I build official 7020 HDMI project with some modification. `set_property IOSTANDARD LVDS_25 [getports {TXi*}] set_property PACKAGE_PIN T5 [get_ports TXi_rd_wait_p]

NET "RXO_RD_WAIT_N" LOC = "H17";

set_property PACKAGE_PIN H18 [get_ports TX_wr_wait_n]`

and set_property PACKAGE_PIN R16 [get_ports {GPIO_N[23]}] set_property PACKAGE_PIN V5 [get_ports {GPIO_P[23]}]

Because TXi_rd_wait_p have to be set with differential pair to solve building error. AND: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.

The bitstream could be booted but still had no HDMI Output. How to reslove this? Thanks.

[peteasa]

@mopplayer - Good that the HDMI video is ok!.. The changes you have made seem not to be related to the hdmi interface so it is possible that the audio problems you have are also in the original parallella/parallella-fpga that is 8 commits ahead of my project and made the change from vivado 2015.2 to 2015.4.2.. or with your conversion to vivado 2017.2.. or with the drivers that you are using with the linux kernel...

@olajep - Can you confirm that the audio part of the fpga works? peteasa/parallella-fpga: Anything be OK parallella/parallella-fpga: HDMI be OK, but Audio causes a kernel crash dump

============= Note that oh tcl scripts have "set scripts_vivado_version 2015.2" and the official hdmi version uses vivado version 2015.4 and the official adi uses 2015.4.2 you are using vivado 2017.2 so expect differences and possible build problems. See - https://github.com/parallella/oh/blob/master/src/parallella/fpga/headless_e16_z7020/system_bd.tcl for reference to vivado 2015.2 and bd:tool_version="2015.4" in https://github.com/parallella/parallella-fpga/blob/2016.11/7020_hdmi/7020_hdmi.srcs/sources_1/bd/elink2_top/elink2_top.bd. See REQUIRED_VIVADO_VERSION "2015.4.2" in the adi libraries https://github.com/analogdevicesinc/hdl/blob/a72873980715a0893c6425bcf850639f468f3124/library/scripts/adi_ip.tcl

The pin property changes you made are different to those published in https://github.com/parallella/oh/blob/master/src/parallella/fpga/parallella_io.xdc so expect problems with the epiphany elink connection.

Kernel crash From @mopplayer: Hi, peteasa. I used corresponding Adi Library and Oh Library with some modifications, and combined source from:

peteasa/parallella-fpga: Anything be OK
parallella/parallella-fpga: HDMI be OK, but Audio be corrupted after log in.
[ 38.367832] Unhandled fault: imprecise external abort (0x406) at 0x000ee1b4 [ 38.373417] pgd = ea188000 [ 38.374799] [000ee1b4] *pgd=2a160831, *pte=2720e75f, *ppte=2720ec7f [ 38.379757] Internal error: : 406 [#1] PREEMPT SMP ARM [ 38.383573] Modules linked in: epiphany [ 38.386080] CPU: 1 PID: 2367 Comm: pulseaudio Not tainted 4.6.0+ #1 [ 38.391038] Hardware name: Xilinx Zynq Platform [ 38.394245] task: ef23b700 ti: ea15e000 task.ti: ea15e000 [ 38.398337] PC is at regmap_mmio_read32le+0x10/0x14 [ 38.401876] LR is at regmap_mmio_read+0x2c/0x5c [ 38.405101] pc : [<c027d9b4>] lr : [<c027db18>] psr: 200a0093 sp : ea15fce0 ip : 00000000 fp : bebb58f8 [ 38.413949] r10: ef19ebe0 r9 : ef2f7e0c r8 : 00000001 [ 38.417857] r7 : ea15fd0c r6 : ea15fd0c r5 : 00000000 r4 : ef0d6740 [ 38.423054] r3 : f095e000 r2 : ea15fd0c r1 : f095e000 r0 : 00000000 [ 38.428271] Flags: nzCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment none [ 38.434169] Control: 18c5387d Table: 2a18804a DAC: 00000051 [ 38.438593] Process pulseaudio (pid: 2367, stack limit = 0xea15e210) [ 38.443625] Stack: (0xea15fce0 to 0xea160000) [ 38.446684] fce0: ef381400 ef381400 00000000 c0278e80 00000001 00000000 ef381400 00000000 [ 38.453541] fd00: 00000001 c027916c ef381400 00000000 ef381400 00000000 00000001 00000001 [ 38.460398] fd20: ea15e000 c0279f5c 00000000 00000000 00000001 00000000 ef0eb510 ef0d6500 [ 38.467255] fd40: 00000001 c0437590 00000000 00000000 00000000 c0437518 ef19d000 ef381000 [ 38.474111] fd60: ef22f500 c042f2e0 ea19f800 000f4240 0000000b 00000008 00000009 c04023e8 [ 38.480968] fd80: 000f4240 ef19d00c 0000000b ffffffff ef19ebe0 00000000 ea15fdd0 ea207a80 [ 38.487825] fda0: ef19ebc8 ea15e000 00000000 ef19ebe0 bebb58f8 c0402618 ef19e800 ef381000 [ 38.494682] fdc0: ea207a80 00000000 ef19e800 c0402704 07400010 00000000 ef23b700 c0040f48 [ 38.501539] fde0: ef19ebe4 ef19ebe4 ea207a80 ef19e800 ef15d5c0 ef383198 ea207a80 ea15e000 [ 38.508395] fe00: ea15ff74 c04028c4 c05e3100 00000000 ef15d5c0 c00d74e8 ef383198 00000010 [ 38.515252] fe20: ea207a80 ef383198 ea207a80 c00d73b0 ea207a88 c00d16e4 00000000 ea15fed0 [ 38.522109] fe40: ea207a80 ffffff9c 00000000 ea15e000 ea15ff74 c00df634 ea15fe80 c00dbcc0 [ 38.528984] fe60: 00000000 00000802 00000000 eec32198 00000041 ea15e000 00000006 fffffdfd [ 38.535822] fe80: eea32800 ea19af40 40045532 00000000 00000002 ef383198 00000000 00000000 [ 38.542679] fea0: ee9e8250 eec31440 00000002 00000012 ea15ff74 00000001 ffffff9c c000efc4 [ 38.549536] fec0: ea15e000 00000000 bebb58f8 c00e0ac4 ee9e8250 eec31440 474edc20 00000008 [ 38.556393] fee0: ef10b019 0000455f 00000000 eec327f8 ef383198 00000101 00000002 00000132 [ 38.563268] ff00: 00000000 00000000 00000000 ea15ff10 bebb55ac c00e2fc0 eec313b8 ea207b48 [ 38.570106] ff20: 00080040 00000012 eeab9218 eeab9200 eeab9240 00080802 00000012 c00ec4dc [ 38.576981] ff40: ef10b000 00000000 00080802 00000002 ffffff9c c000efc4 00000012 00080802 [ 38.583838] ff60: ef10b000 c00d28d8 00000011 00000011 ea207b40 00000802 40040000 00000006 [ 38.590676] ff80: 00000100 00000001 bebb58f8 ffffffff bebb5604 00000004 00000005 c000efc4 [ 38.597552] ffa0: ea15e000 c000ee00 ffffffff bebb5604 bebb55dc 00080802 04000000 000d7c10 [ 38.604390] ffc0: ffffffff bebb5604 00000004 00000005 adc23000 00000000 bebb55dc bebb58f8 [ 38.611265] ffe0: 00000000 bebb55b0 00000000 b6cc17c2 800a0030 bebb55dc 2fffd861 2fffdc61 [ 38.618122] [<c027d9b4>] (regmap_mmio_read32le) from [<c027db18>] (regmap_mmio_read+0x2c/0x5c) [ 38.625421] [<c027db18>] (regmap_mmio_read) from [<c0278e80>] (_regmap_read+0x78/0xb0) [ 38.632001] [<c0278e80>] (_regmap_read) from [<c027916c>] (_regmap_update_bits+0x64/0xc0) [ 38.638858] [<c027916c>] (_regmap_update_bits) from [<c0279f5c>] (regmap_update_bits_base+0x4c/0x70) [ 38.646673] [<c0279f5c>] (regmap_update_bits_base) from [<c0437590>] (axi_spdif_startup+0x78/0x84) [ 38.654323] [<c0437590>] (axi_spdif_startup) from [<c042f2e0>] (soc_pcm_open+0xcc/0x7ac) [ 38.661087] [<c042f2e0>] (soc_pcm_open) from [<c0402618>] (snd_pcm_open_substream+0x48/0x90) [ 38.668202] [<c0402618>] (snd_pcm_open_substream) from [<c0402704>] (snd_pcm_open+0xa4/0x1cc) [ 38.675428] [<c0402704>] (snd_pcm_open) from [<c04028c4>] (snd_pcm_playback_open+0x3c/0x5c) [ 38.682450] [<c04028c4>] (snd_pcm_playback_open) from [<c00d74e8>] (chrdev_open+0x138/0x164) [ 38.689565] [<c00d74e8>] (chrdev_open) from [<c00d16e4>] (do_dentry_open+0x1d8/0x2ec) [ 38.696090] [<c00d16e4>] (do_dentry_open) from [<c00df634>] (path_openat+0x3c4/0xd60) [ 38.702597] [<c00df634>] (path_openat) from [<c00e0ac4>] (do_filp_open+0x30/0x7c) [ 38.708753] [<c00e0ac4>] (do_filp_open) from [<c00d28d8>] (do_sys_open+0x110/0x1b0) [ 38.715094] [<c00d28d8>] (do_sys_open) from [<c000ee00>] (ret_fast_syscall+0x0/0x3c) [ 38.721508] Code: e5903000 e0831001 e5910000 f57ff04f (e12fff1e) [ 38.726263] ---[ end trace b0d4cc977420b666 ]--- [ 38.729563] note: pulseaudio[2367] exited with preempt_count 1

Maybe it still had some mismatch about official release.

[mopplayer]

@peteasa Hi, peteasa. Only REQUIRED_VIVADO_VERSION "2015.4.2" of AdiLib would cause errors, and those cases had been modified to 2017.2, so those cases were built correctly and generated bitstream.

But official case would fail about audio. The pin about SPDIF had no changed. I didn't use the master of Oh Library, it would fail. By using https://github.com/parallella/oh/tree/e7abddbcb5081b70daa10c5a42bbbdb0b5bb5742 set_property PACKAGE_PIN Y16 [get_ports HDMI_SPDIF]

It is strange...

[olajep]

Can you confirm that the audio part of the fpga works? peteasa/parallella-fpga: Anything be OK parallella/parallella-fpga: HDMI be OK, but Audio causes a kernel crash dump

Yes, a slightly modified parallella-fpga was used to build the bitstreams for the Parabuntu 2016.11 HDMI images. They work for both the z7010 and z7020.

https://github.com/parallella/parallella-fpga/ branch 2016.11 commit 5ec417b3f8cdf3ef278679b10333c78f7276060b

You might want to merge that branch

// Ola

[jschiefer]

It appears that the related changes in olajep/oh, branch hdl_2016_r1 made by @olajep on Dec. 5, 2016 (the last 5 commits on that branch) were never merged up into parallella/oh. Is there a specific reason for this, or did it just fall through the cracks? I am trying to bring parallella-fpga and its dependencies up to Vivado 2018.2, and I want to make sure I use the latest versions of everything.

[peteasa]

Feel free to work with hdl_2016_r1 and the latest parallella linux release.

The parent project to parallella-fpga (see elink-redesign branch and https://github.com/peteasa/parallella/wiki) uses several sub projects one of which is parallella-fpga. As a set these are self consistent and will build a working system. If I am to take the changes made on oh into parallella-fpga then I would also want to update parallella-yocto (https://github.com/peteasa/parallella-yoctobuild) in particular move to the latest parallella linux release. I do not have the time to do this and to test that the whole multi project environment is working so I left it as it is. So the parallella-fpga (@abc1d5) and associated oh project (@4c6cdc) part of the project is now behind the latest available and would not work with the latest parallella linux release but would still work with the custom linux release built using yocto provided by parallella-yoctobuild. The update required is more than a little bit of work.