Support for Zba, Zbb, and similar XTHead instructions.

[brucehoult]

This is great!

Unfortunately I can't use it on my Lichee Pi 4A (TH1520 SoC, THead C910 cores) because before it gets to my code:

disInstr(riscv64): unhandled instruction 0x01A0000B

That's th.sync.i. Which is probably only the first of many such instructions, including lots from XTheadBa, XTheadBb etc, even though my own code is compiled for generic RV64GC.

Fortunately it works fine on my VisionFive 2, as long as I don't compile my code with Zba or Zbb. If I do then it fails (on my current program of interest) with:

disInstr(riscv64): unhandled instruction 0x20BECE33

... which is sh2add.

Any plans to add support for these?

I could maybe figure out how to add just the ones my code is actually using. I haven't looked at the internals yet.

[brucehoult]

It also doesn't support the standard fence.i instruction :-(

RISCV64 front end: standard
disInstr(riscv64): unhandled instruction 0x0000100F
disInstr(riscv64): 0000'0000 0000'0000 0001'0000 0000'1111

[mingyuan-xia]

This is great!

Unfortunately I can't use it on my Lichee Pi 4A (TH1520 SoC, THead C910 cores) because before it gets to my code:

disInstr(riscv64): unhandled instruction 0x01A0000B

That's th.sync.i. Which is probably only the first of many such instructions, including lots from XTheadBa, XTheadBb etc, even though my own code is compiled for generic RV64GC.

Fortunately it works fine on my VisionFive 2, as long as I don't compile my code with Zba or Zbb. If I do then it fails (on my current program of interest) with:

disInstr(riscv64): unhandled instruction 0x20BECE33

... which is sh2add.

Any plans to add support for these?

I could maybe figure out how to add just the ones my code is actually using. I haven't looked at the internals yet.

Is it because of the prebuilt libraries that have XTHead* instructions being linked to your program?

[petrpavlu]

My initial plan for the port was to target RV64GC, get this initial work upstream, and only then start adding support for more RISC-V extensions as they are introduced.

With new hardware beginning to implement the RVA22 and RVA23 profiles, I guess this approach no longer works. To keep the port useful, it will be necessary to start implementing support for these extensions.

Hopefully, most of the relevant extensions can be added in Valgrind in such a way that their code is limited to the RISC-V implementation and doesn't need significant changes in the rest of the project. Otherwise, this could further complicate upstreaming of the port.

Zba and Zbb are already mandatory in RVA22 and therefore should be certainly added.

As for the Xthead* extensions, I'm not familiar with them and currently have no plans to add support for them.

[mingyuan-xia]

Would it be nice to have a few more columns next to the UT status for RVA profiles? I can PR a simple draft for that.