Magma 0.9

[phanrahan]

Tentative features for next major release of Magma

• [ ] New type system
  • [x] bracket syntax Bits[n] instead of Bits(n)
  • [x] product types
  • [ ] sum types
  • [x] Consistent with hwtypes
• [ ] Make @combinational and @sequential the preferred way to generate circuits
  • [ ] Polymorphism vs static typing
  • The plan is to implement an analysis pass that discovers polymorphic code and raises and error. In the future, if we decide to add polymorphism, this pass will provide the basis for an implementation. Until then, we will force the user to rewrite their code in a way that effectively duplicates code for handling different types, which forces them to acknowledge the fact that their code is creating extra hardware (rather than having a polymorphic operator implicitly compiled into two different functional units). This design allows a polymorphic layer to be implemented on top of magma, giving magma a simple, concise, precise semantics.
  • [x] Macro story
• [x] Add a mode to compile circuit combinational/sequential directly to verilog using kratos and pass through the black box modules to coreir
• [ ] Capture Python variable names for magma values(wires)/instances and pass through to verilog to improve debuggability
• [ ] Better coreir integration
  • [ ] Depreciate mantle implementations of primitives on FPGAs
  • [ ] Mantle generators called from coreir
• [x] CoreIR verilogAST-based backend to improve readability of generated verilog: https://github.com/rdaly525/coreir/pull/770
• [ ] Resource sharing optimizations
  • [ ] https://github.com/StanfordAHA/lassen/pull/131
  • [ ] https://github.com/StanfordAHA/lassen/pull/132
• [ ] Comprehensive tests of the primitives
  • [ ] Formulate test plan
  • [ ] hwtypes implementation of primitives to test against
• [x] Uniquification
• [x] New generator framework (generators as types/classes) - experimental
• [x] Circuit editing API (for gemstone) - experimental
• [x] Updated magmathon (Pat)
  • [x] Default should not depend on ice40

[leonardt]

I added two things to start making things more concrete.

For "better coreir integration", one thing that I have been thinking about:

Add a mode to compile circuit combinational/sequential directly to verilog using veriloggen and pass through the black box modules to coreir

This would improve the output verilog without having to reconstruct structure (if statements) from the netlist format

For " Consistent mantle implementations and tests"

hwtypes implementation of mantle to test against

@cdonovick brought up that we could provide one-to-one magma/hwtypes implementations for mantle, we could use the hwtypes version for generating simulation vectors and formal (verify the mantle generated RTL is equivalent to the SMT)

[phanrahan]

Good comments. Thanks.

[phanrahan]

Caleb made the suggestion that we simplify the system as we move towards full support for coreir.

The suggestion was to move all the hwtypes/coreir primitives to magma. The goal is to build is to tightly integrate these primitives into magma. A secondary goal is to simplify the mantle implementation, which is complicated because the mantle primitives do mapping.

The new mantle would just contain functions built on the primitives, such as counters, shift registers, fifos, etc.