coreir mantle implementation

[phanrahan]

The following functions are not implemented in coreir.

• LUT
  • LUT1
  • LUT2
  • LUT3
  • LUT4
• MUX
  • Mux2
  • Mux4
  • Mux8
  • Mux16
• FF
  • SRFF
  • RSFF
  • JKFF
  • TFF
• FullAdder
• HalfAdder

[phanrahan]

I added implementations of the Mux2, Mux4, Mux8 and Mux16.

[phanrahan]

Added FullAdder and HalfAdder.

[phanrahan]

The coreir LSR and ASR circuits have a different type signature than the mantle implementations.

Mantle uses

Mux(I : In(Bits(width)), S: In(Bits(clog2(width)), O: Out(Bits(width))

coreir uses

Mux(I : In(Bits(width)), S: In(Bits(width), O: Out(Bits(width))

We need to standardize.

[leonardt]

I raised an issue about this awhile back. @rdaly525 seemed to feel that the interface should be width for the select, similar to the shift assembly instruction. I think I originally felt that clog2 was better since it enforces precise constraints on the semantics of the shift instruction. I'm not sure what allowing the width to be width instead of clog2(width) affords you besides convenience. It makes sense from the ISA perspective because all instructions use, say, 32-bit registers for their inputs, but in the actual hardware it might be a better decision to constrain the inputs to the valid semantic range.

[phanrahan]

I think the clog2 version is better for a hardware interface since it seems low-level and accurate. For example, that is the way the selector in a Mux is typed.

[leonardt]

Okay, for now we can have a wrapper in magma that zexts the clog2 interface to match the coreir interface. We'll have to convince @rdaly525 to update the coreir primitive definitions. One question, do we know if SMT-LIB places any constraints on the width of the argument?

[rdaly525]

According to the QF bitvector definitions, the operands are the same width. http://smtlib.cs.uiowa.edu/logics-all.shtml#QF_BV. I kept the same semantics. This also allows us to be similar to any normal ISA like RISC-V.