Open mpFPGA opened 6 years ago
Hi I certainly encountered such a design, but the one given in the repository should work fine. As stated in the doc, the design was compiled with 2016.3 . During my thesis I also ran some iterations with 2017.1 (I think) and I got some results that did not convince me as I remember.
It looks like it isn't using its available DSP blocks and tries to generate them with logic for some reasons. I would investigate that. Maybe this can be achieved in 2017.4 in another way...
Thanks, I'll concentrate my efforts to figure out why some pragmas are ignored
Hi Philippe, I'm trying to implement your design on a ZCU102 board using SDSoC 2017.4. I am experiencing some issues with the acceleration of conv3x3, since the required number of LUTs is greater than the available resources, as shown in the following image Moreover, it seems that Vivado HLS is ignoring pragmas for DSP usage, also the one inserted by you (#pragma HLS RESOURCE variable=out core=AddSub_DSP), giving error in this form:
WARNING: [SYN 201-303] Cannot apply functional unit assignment of 'AddSub_DSP' (/xilinx/workspace/obj_det/src/hw_convs.c:640->/xilinx/workspace/obj_det/src/hw_convs.c:404) on 'select' operation ('p_load_1', /xilinx/workspace/obj_det/src/hw_convs.c:640->/xilinx/workspace/obj_det/src/hw_convs.c:404) due to incompatible operation sets.
Did you experienced similar problems or do you have any ideas to solve it? Thanks for your attention