Implement cycle-accurate timing in the emulator

philpax / skiron

Skiron is a basic 32-bit RISC-inspired CPU architecture.

MIT License

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Implement cycle-accurate timing in the emulator #1

Open philpax opened 9 years ago

philpax commented 9 years ago

Would necessitate the addition of a cache, amongst other things. Instruction execution would be clearly separated into its constituent pipeline stages; fetch, decode, and execute (and others, if necessary).

philpax commented 8 years ago

Investigate the use of fibers.