Closed jmaksymowicz closed 2 months ago
7 460 tests +724 6 745 :white_check_mark: +695 39m 33s :stopwatch: + 6m 14s 420 suites ± 0 715 :zzz: + 75 1 files ± 0 0 :x: - 46
Results for commit b1884db6. ± Comparison against base commit 47ac14ed.
:recycle: This comment has been updated with latest results.
Reverted change that activated L2 cache - it caused stability problems in some tests. I haven't found the reason for it yet. Because it's not necessary for SMP I think we should do it in a different PR.
EDIT: it didn't help, only reduced frequency of failing
Allows tasks to be scheduled on both CPU cores on zynq7000 platform.
Description
NOTE: the corresponding PR in PLO must be merged first - otherwise on zynq7000 kernel will hang waiting for other CPU cores which will never start.
Code is capable of detecting number of available CPUs at runtime, the
NUM_CPUS
constant is used as maximum number of CPUs to prepare for.One change was made not related to SMP: size of page directories was changed from
0x4000
bytes to0x2000
bytes, as the upper half was unnecessaryMemory attributes were changed in common armv7a code, which affects imx6ull (but should not cause significant change).
Using SMP on armv7a9-zynq7000-qemu causes drastic slowdown (about 4x-5x slower) when executing single-core workloads. This is because under QEMU the idle thread creates a lot of load on the host CPU, as well as contention on the timer spinlock. This slowdown does not occur on real hardware. For this reason I suggest limiting QEMU to emulating only one core, as we can test SMP configurations on real hardware.
Motivation and Context
Types of changes
How Has This Been Tested?
Checklist:
Special treatment