phymooc / learn-verification

0 stars 0 forks source link

System Verilog #3

Open phymo opened 2 years ago

phymo commented 2 years ago

1. Data Type

image

0 | Logic state 0 - variable/net is at 0 volts -- | -- 1 | Logic state 1 - variable/net is at some value > 0.7 volts x or X | Logic state X - variable/net has either 0/1 - we just don't know z or Z | Logic state Z - net has high impedence - maybe the wire is not connected and is floating

4-state value vs 2-state value

when 4 state value is converted to 2 state value, X/Z will be set to 0

phymo commented 2 years ago

https://www.chipverify.com/systemverilog/

phymo commented 1 year ago

vector

Array

  1. unpacked vs packed arrays