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physical-computation / Sail-RV32I-common

Common files for the Sail RISC-V processor.
MIT License
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Possible timing issue #10

Closed rjlv2 closed 5 years ago

rjlv2 commented 5 years ago

Possible timing issue to look into, processor stops working on the iCE40 UP FPGA when wb_mux is moved back to the EX stage.

rjlv2 commented 5 years ago

I think this is something to do with placement of the data memory. Nextpnr reported an error which arachne-pnr didn't catch. The error was subsequently fixed, and the problem went away.