Look into bottleneck in memory access

physical-computation / Sail-RV32I-common

Common files for the Sail RISC-V processor.

MIT License

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Look into bottleneck in memory access #17

Closed rjlv2 closed 5 years ago

rjlv2 commented 6 years ago

Bottleneck during memory access. The processor will run at 12MHz for programs that require only register access, and only 6MHz for programs that require data memory access as well. The registers use block RAM and the data memory uses SPRAm which are available on the iCE40 Ultra Plus FPGA.

For comparison the DE0 nano implementation is capable of running even above 50MHz.

rjlv2 commented 5 years ago

Memory modules have been updated and is running at 12MHz. Icetime gives an estimate of (around) 13.42 MHz.