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physical-computation / Sail-RV32I-common

Common files for the Sail RISC-V processor.
MIT License
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Implement CSR #18

Open rjlv2 opened 6 years ago

rjlv2 commented 6 years ago

Need to implement and test CSR instructions.

rjlv2 commented 5 years ago

Currently simple registers act as placeholders for the actual implementation.

harrysarson commented 5 years ago

Worth noting: in the latest spec version (https://github.com/riscv/riscv-isa-manual/releases/latest) CSR registers are no longer in the base RV32I so we could possibly justify not supporting them.

I quote from chapter 9:

The counters and timers are no longer considered mandatory parts of the standard base ISAs, and so the CSR instructions required to access them have been moved out of the base ISA chapter into this separate chapte