Merge RV32_I and narvie's cpu.v

[harrysarson]

The main file that we need to reconcile is cpu.v.

I am currently building narvie successfully but using my cpu.v. It would be great if we were able to use the same cpu.v. Alternatively, we could move much of the common logic out of cpu.v and into a file that we could share.

Here is the diff between your and my cpu.v:

diff --git a/RV32I_common/verilog/cpu.v b/cpu.v
index 23c2d63..35e7329 100755
--- a/RV32I_common/verilog/cpu.v
+++ b/cpu.v
@@ -9,7 +9,14 @@ module cpu(
            data_mem_WrData,
            data_mem_memwrite,
            data_mem_memread,
-           data_mem_sign_mask
+           data_mem_sign_mask,
+           regfile_do_write,
+           regfile_write_addr,
+           regfile_write_data,
+           regfile_read_address0,
+           regfile_read_address1,
+           regfile_read_data0,
+           regfile_read_data1
        );

    //Input Clock
@@ -27,6 +34,15 @@ module cpu(
    output data_mem_memread;
    output[3:0] data_mem_sign_mask;

+   //Register File
+   output regfile_do_write;
+   output[4:0] regfile_write_addr;
+   output[31:0] regfile_write_data;
+   output[4:0] regfile_read_address0;
+   output[4:0] regfile_read_address1;
+   input[31:0] regfile_read_data0;
+   input[31:0] regfile_read_data1;
+
    //Program Counter
    wire[31:0] pc_mux0;
    wire[31:0] pc_in;
@@ -58,8 +74,6 @@ module cpu(

    //Decode stage
    wire [31:0] cont_mux_out; //control signal mux
-   wire[31:0] regA_out;
-   wire[31:0] regB_out;
    wire[31:0] imm_out;
    wire[31:0] RegA_mux_out;
    wire[31:0] RegB_mux_out;
@@ -172,16 +186,6 @@ module cpu(
            .out(cont_mux_out)
        );

-   regfile register_files( 
-           .clk(clk), 
-           .write(ex_mem_out[2]), //mem_wb_out[2]
-           .wrAddr(ex_mem_out[142:138]), //mem_wb_out[104:100]
-           .wrData(reg_dat_mux_out), 
-           .rdAddrA(inst_mux_out[19:15]), //if_id_out[51:47] //inst_mux_out[19:15]
-           .rdDataA(regA_out), 
-           .rdAddrB(inst_mux_out[24:20]), //if_id_out[56:52] //inst_mux_out[24:20]
-           .rdDataB(regB_out)
-       );

    imm_gen immediate_generator(
            .inst(if_id_out[63:32]),
@@ -209,27 +213,27 @@ module cpu(
        );

    mux2to1 RegA_mux(
-           .input0(regA_out),
+           .input0(regfile_read_data0),
            .input1({27'b0, if_id_out[51:47]}),
            .select(CSRRI_signal),
            .out(RegA_mux_out)
        );

    mux2to1 RegB_mux(
-           .input0(regB_out),
+           .input0(regfile_read_data1),
            .input1(rdValOut_CSR),
            .select(CSRR_signal),
            .out(RegB_mux_out)
        );

-   mux2to1 RegA_AddrFwdFlush_mux( //TODO cleanup
+   mux2to1 RegA_AddrFwdFlush_mux(
            .input0({27'b0, if_id_out[51:47]}),
            .input1(32'b0),
            .select(CSRRI_signal),
            .out(RegA_AddrFwdFlush_mux_out)
        );

-   mux2to1 RegB_AddrFwdFlush_mux( //TODO cleanup
+   mux2to1 RegB_AddrFwdFlush_mux(
            .input0({27'b0, if_id_out[56:52]}),
            .input1(32'b0),
            .select(CSRR_signal),
@@ -335,10 +339,10 @@ module cpu(
            .out(wb_mux_out)
        );

-   mux2to1 reg_dat_mux( //TODO cleanup
-           .input0(mem_regwb_mux_out), //wb_mux_out
-           .input1(id_ex_out[43:12]), //ex_mem_out[40:9]
-           .select(ex_mem_out[0]), //mem_wb_out[0]
+   mux2to1 reg_dat_mux(
+           .input0(wb_mux_out),
+           .input1(ex_mem_out[40:9]),
+           .select(mem_wb_out[0]),
            .out(reg_dat_mux_out)
        );

@@ -422,15 +426,6 @@ module cpu(
            .out(pc_mux0)
        );

-   wire[31:0] mem_regwb_mux_out; //TODO copy of wb_mux but in mem stage, move back and cleanup
-   //A copy of the writeback mux, but in MEM stage //TODO move back and cleanup
-   mux2to1 mem_regwb_mux( 
-           .input0(mem_csrr_mux_out),
-           .input1(data_mem_out),
-           .select(ex_mem_out[1]),
-           .out(mem_regwb_mux_out)
-       );
-   
    //OR gate assignments, used for flushing
    assign decode_ctrl_mux_sel = pcsrc | mistake_trigger;
    assign inst_mux_sel = pcsrc | predict | mistake_trigger | Fence_signal;
@@ -445,5 +440,12 @@ module cpu(
    assign data_mem_memread = ex_cont_mux_out[5];
    assign data_mem_sign_mask = id_ex_out[150:147];

+   //Register File Connections
+   assign regfile_do_write = mem_wb_out[2];
+   assign regfile_write_addr = mem_wb_out[104:100];
+   assign regfile_write_data = reg_dat_mux_out;
+   assign regfile_read_address0 = inst_mux_out[19:15]; //if_id_out[51:47] //inst_mux_out[19:15]
+   assign regfile_read_address1 = inst_mux_out[24:20]; //if_id_out[56:52] //inst_mux_out[24:20]
+
 endmodule