Currently data memory is implemented using a state machine and stalls to the processor clock. It might be possible to implemented read and writes in 1 clock cycle, but that means constraining a lot of logic operations to run in 1 clock cycle. Might be worth checking the impact on timing.
Currently data memory is implemented using a state machine and stalls to the processor clock. It might be possible to implemented read and writes in 1 clock cycle, but that means constraining a lot of logic operations to run in 1 clock cycle. Might be worth checking the impact on timing.