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picosonic / D3

Dizzy3
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Add support for SW memory on BBC B+ #11

Closed picosonic closed 1 year ago

picosonic commented 1 year ago

Current detection of SWRAM just tries to ROMSEL to each bank 0..F and then use the first one which is writeable, however this doesn't seem to work on the B+

picosonic commented 1 year ago

SWRAM defaults

A/B = None (mapped to 12/13/14) FAIL B/Opus DDOS = (13) OK B/Opus CHALLENGER (256) = (13) FAIL B/Opus CHALLENGER (512) = (13) FAIL B+ (64) = ONLY 12k of shadow RAM (128) FAIL B PLUS (112) = (??) OK B+ 128 = (0,1,12,13) OK B+ Integra-B (256) = (??) FAIL Master 128 = (4,5,6,7) OK Master compact = (4,5,6,7)

A/B = OK when SWRAM configured

picosonic commented 1 year ago

These are the results of detecting sideways RAM on a few emulators, in their default configurations, just using FE30 (ROMSEL) and a test write ..

beebjit

jsbeeb

beebem

b2

picosonic commented 1 year ago

The sideways RAM I have on my Beeb is via the Watford Electronics ROM/RAM board.

It would seem that the SWRAM needs to be selected via standard ROMSEL, then you also need to write (any value) to &FF30+slot to make it writeable.

Wouter reported not to have tested these boards yet. But there is code in swrtype to detect these boards.

Interesting that you can also make the RAM on these boards read only. e.g. to write protect all the sockets, ?&FF38=0

picosonic commented 1 year ago

BooBip 32k RAM/ROM hardware

The BBC hardware maps the ROM sockets from left to right as ROM 12, 13, 14 & 15. The paged ROMs appear in the 64kB address space of the 6502 processor at addresses &8000 - &BFFF.

Each ROM/RAM board can select one of four banks. Two 16kB RAM banks and upto two 16kB ROM banks. So depending on which socket the module is installed in you will get the following paged ROM allocations.

From left to right: IC52 : Banks 0=RAM, 4=RAM, 8=ROM, 12=ROM IC58 : Banks 1=RAM, 5=RAM, 9=ROM, 13=ROM IC100 : Banks 2=RAM, 6=RAM, 10=ROM, 14=ROM IC100 : Banks 3=RAM, 7=RAM, 11=ROM, 15=ROM

RAM write protect (WP) is software controlled so there are no physical write protect switches to mount. WP is handled by the Atmel programmable logic device on the boards. Commands are written to the paged ROM register at address &FE30. Each 16kB RAM bank has a separate write protect.

Set write protect command: &2x - where x is the memory bank number in the BBC from 0-F hex

Clear write protect command: &3x - where x is the memory bank number in the BBC from 0-F hex

10 P%=&C00 20 [.wpset:ORA #&20:STA &FE30:LDA &F4:STA &FE30:RTS:] 30 [.wpclr:ORA #&30:STA &FE30:LDA &F4:STA &FE30:RTS:] 40 INPUT A% 50 CALL wpset 60 INPUT A% 70 CALL wpclr

Connect the ROMSEL spring clip to IC26 (left of the CPU) pin 5. (Pin 1 is top left count anticlockwise). Connect the WDS spring clip to IC73 (under analogue port) pin 24. (Pin 28 is top right count clockwise).

If IC26 or IC73 are inconvenient then alternate pins for the clips can be used. ROMSEL

IC26 pin 5 (74LS139 left of 6502 CPU)
IC76 pin 9 (74LS163 under keyboard ribbon cable)

WDS

IC73 pin 24 (uPD7002 next to analogue port)
IC77 pin 8 (74LS00 near the copyright logo where it says the issue number)
IC78 pin 10 (8271 above keyboard connector)
picosonic commented 1 year ago

On the B+ ..

the 20k shadow screen is &3000 to &7FFF the 12k paged RAM is &8000 to &AFFF

shadow modes are selected by adding 128 to mode number, this then allows memory from PAGE up to &7FFF to be used for code/data without effecting on-screen.

Enabling shadow *SHADOW 1

Disabling shadow *SHADOW

Hard break / reset will default to shadow off

picosonic commented 1 year ago

From pop-beeb, swapping shadow buffers

; in double buffer mode, both display & main memory swap, but point to the opposite memory .shadow_swap_buffers { lda &fe34 eor #1+4 ; invert bits 0 (CRTC) & 2 (RAM) sta &fe34 rts }

picosonic commented 1 year ago

From pop-beeb

\ Ensure MAIN RAM is writeable

LDA &FE34:AND #&FB:STA &FE34

\ Ensure SHADOW RAM is writeable

LDA &FE34:ORA #&4:STA &FE34
picosonic commented 1 year ago

From pop-beeb

\ Setup SHADOW buffers for double buffering

; we set bits 0 and 2 of ACCCON, so that display=Main RAM, and shadow ram is selected as main memory
lda &fe34
and #255-1  ; set D to 0
ora #4      ; set X to 1
sta &fe34
picosonic commented 1 year ago

There's a difference between which screen RAM is accessed by the VDU driver and which screen RAM is actually being displayed. This, for example, allows one image to be displayed whilst another image is being created or updated, and then displayed when the updating is completed.

Bit 2 of ACCCON (&FE34) determines which bank is paged in, and bit 0 determines which bank is being displayed. See Master Reference Manual F2.3 (available on Chris's Acorns and elsewhere).

It might be better to use operating system calls to do the bank switching, the MOS provides several OSBYTE/FX calls:

OSBYTE 108 - page in main or shadow RAM OSBYTE 112 - set which bank is updated by the VDU driver OSBYTE 113 - set which bank is being displayed OSBYTE 114 - force or unforce use of shadow RAM on next mode change.

It's perfectly possible to access RAM this way - my untitled dungeon game moves large chunks of the screen about from sideways ram. However - I don't ever read the ACCCON register - and I wonder if that's the problem.

The way I have the memory set up is I change to a shadow mode (130) then use osbyte 108 to enable and disable writing to the shadow screen before paging in the SWROM I want to use and calling code in that. Everything else (VDU drivers and Basic memory) is left as is.

picosonic commented 1 year ago

I'm only going to initially support SWRAM that I'm able to detect with ROMSEL method