..then the RST signal appears to be permanently held low, regardless of input.
In the case of jt12_reg_ch.v, i discovered that if I remove enough of the assignments within the else begin block, RST works. Particularly, if I remove enough of the assignments such that there are no more than four bits being assigned in total, RST works.
e.g. reg_rl and reg_ams can both be assigned, but if reg_pms is assigned, the others must be removed.
Gowin FPGA Designer produces no warnings or errors which appear to be related to the issue.
Issue seems to be more broad than just this. On the GW2AR/Tang Nano 20K, everything runs flawlessly. The GW5A/Tang Primer 25K, however, exhibits all kinds of weirdness.
If the
if (rst)
checks are kept in code at the following locations: https://github.com/planetarian/jt12/blob/7255be596de03fd7c9daaa438fb9d12a97c09bd8/hdl/jt12_mmr.v#L211 https://github.com/planetarian/jt12/blob/7255be596de03fd7c9daaa438fb9d12a97c09bd8/hdl/jt12_reg_ch.v#L105..then the RST signal appears to be permanently held low, regardless of input.
In the case of
jt12_reg_ch.v
, i discovered that if I remove enough of the assignments within theelse begin
block, RST works. Particularly, if I remove enough of the assignments such that there are no more than four bits being assigned in total, RST works. e.g.reg_rl
andreg_ams
can both be assigned, but ifreg_pms
is assigned, the others must be removed.Gowin FPGA Designer produces no warnings or errors which appear to be related to the issue.