Closed isnadh closed 2 years ago
arduino12
commented
3 years ago Hi,
I just started adding support for the N76E003 board :) Here is the example project I just made! I made 2 examples: gpio_test and uart_test_with_interrupt and they both work great.
@ivankravets Please let me know how can I add this local N76E003 board and upload-script and api to the awesome global PlatformIO- I wrote some TODOs but I am not so sure how to do it..
Arad :)
snovotill
commented
3 years ago Here is a Nuvoton board file:
{ "build": { "core": "naked", "extra_flags": "-DN76E003 -DNAKED_ARCH_MCS51 -DNAKED_MCS51_N76E003", "f_cpu": "16000000L", "size_iram": 256, "size_xram": 768, "size_code": 18432, "size_heap": 128, "mcu": "n76e003", "cpu": "mcs51" }, "frameworks": [], "upload": { "maximum_ram_size": 1024, "maximum_size": 18432, "protocol": "nuvoprog", "nuvoprog_protocol": "n76e003", "protocols": [ "nuvoprog" ] }, "name": "Generic N76E003", "url": "https://www.nuvoton.com/products/microcontrollers/8bit-8051-mcus/low-pin-count-8051-series/n76e003/", "vendor": "Nuvoton" }
snovotill
commented
3 years ago And here is N76E003.h
// Suitable for use with all N76E003 series MCU. // This header file was verified against the official Nuvoton BSP // however it corrects a number of Nuvoton BSP inconsistencies. // After this file is included you don't have to include "reg51.h". // Comments begining with /// indicate non 8051/8052 extensions. // Comments beginning with //- indicate 8051 and //+ indicate 8052. // Comments begining with //= indicate defacto standard aliases. // X means undefined, U means unchanged, C means config dependent.
//SFR DEFINITION | NOTE | POR RESET VALUE | DESCRIPTION
SFR(P0, _P0); //- 1111'1111 Port 0 SBIT( P0_0, _P0, 0); //- SBIT( P00, _P0, 0); //= SBIT( MOSI, _P0, 0); /// SBIT( T1, _P0, 0); /// SBIT( P0_1, _P0, 1); //- SBIT( P01, _P0, 1); //= SBIT( MISO, _P0, 1); /// SBIT( P0_2, _P0, 2); //- SBIT( P02, _P0, 2); //= SBIT( RXD_1, _P0, 2); /// SBIT( P0_3, _P0, 3); //- SBIT( P03, _P0, 3); //= SBIT( P0_4, _P0, 4); //- SBIT( P04, _P0, 4); //= SBIT( P0_5, _P0, 5); //- SBIT( P05, _P0, 5); //= SBIT( T0, _P0, 5); /// SBIT( P0_6, _P0, 6); //- SBIT( P06, _P0, 6); //= SBIT( P0_7, _P0, 7); //- SBIT( P07, _P0, 7); //=
SFR(SP, _SP); //- 0000'0111 Stack pointer
SFR(DPL, _DPL); //- 0000'0000 Data pointer low byte
SFR(DPH, _DPH); //- 0000'0000 Data pointer high byte
SFR(RCTRIM0, _RCTRIM0); /// 0000'0000 Internal RC trim value high byte
SFR(RCTRIM1, _RCTRIM1); /// 0000'0000 Internal RC trim value low byte
SFR(RWK, _RWK); /// 0000'0000 Self wake-up timer reload byte
//SFR(PCON, _PCON); //- 0XXX'0000 Power Control (8051) SFR(PCON, _PCON); /// 0001'0000 Power Control (N76E003)
SFR(TCON, _TCON); //- 0000'0000 Timer/Counter Control SBIT(IT0, _TCON, 0); //- SBIT(IE0, _TCON, 1); //- SBIT(IT1, _TCON, 2); //- SBIT(IE1, _TCON, 3); //- SBIT(TR0, _TCON, 4); //- SBIT(TF0, _TCON, 5); //- SBIT(TR1, _TCON, 6); //- SBIT(TF1, _TCON, 7); //-
SFR(TMOD, _TMOD); //- 0000'0000 Timer/Counter Mode Control
SFR(TL0, _TL0); //- 0000'0000 Timer/Counter 0 Low Byte
SFR(TL1, _TL1); //- 0000'0000 Timer/Counter 1 Low Byte
SFR(TH0, _TH0); //- 0000'0000 Timer/Counter 0 High Byte
SFR(TH1, _TH1); //- 0000'0000 Timer/Counter 1 High Byte
SFR(CKCON, _CKCON); /// 0000'0000 Clock control
SFR(WKCON, _WKCON); /// 0000'0000 Self wake-up timer control
SFR(P1, _P1); //- 1111'1111 Port 1 SBIT( P1_0, _P1, 0); //- SBIT( P10, _P1, 0); //= //SBIT( T2, _P1, 0); //+ Software defined on N76E003 SBIT( SPCLK, _P1, 0); /// SBIT( P1_1, _P1, 1); //- SBIT( P11, _P1, 1); //= //SBIT( T2EX, _P1, 1); //+ Software defined on N76E003 SBIT( P1_2, _P1, 2); //- SBIT( P12, _P1, 2); //= SBIT( P1_3, _P1, 3); //- SBIT( P13, _P1, 3); //= SBIT( P1_4, _P1, 4); //- SBIT( P14, _P1, 4); //= SBIT( FB, _P1, 4); /// SBIT( P1_5, _P1, 5); //- SBIT( P15, _P1, 5); //= SBIT( SS, _P1, 5); /// SBIT( P1_6, _P1, 6); //- SBIT( P16, _P1, 6); //= SBIT( TXD_1, _P1, 6); /// SBIT( P1_7, _P1, 7); //- SBIT( INT1, _P1, 7); /// SBIT( P17, _P1, 7); //=
SFR(SFRS, _SFRS); /// TA 0000'0000 SFR page selection
SFR(CAPCON0, _CAPCON0); /// 0000'0000 Input capture control 0
SFR(CAPCON1, _CAPCON1); /// 0000'0000 Input capture control 1
SFR(CAPCON2, _CAPCON2); /// 0000'0000 Input capture control 2
SFR(CKDIV, _CKDIV); /// 0000'0000 Clock divider
SFR(CKSWT, _CKSWT); /// TA 0011'0000 Clock switch
SFR(CKEN, _CKEN); /// TA 0011'0000 Clock enable
SFR(SCON, _SCON); //- 0000'0000 Serial Port 0 Control SBIT( RI, _SCON, 0); //- SBIT( TI, _SCON, 1); //- SBIT( RB8, _SCON, 2); //- SBIT( TB8, _SCON, 3); //- SBIT( REN, _SCON, 4); //- SBIT( SM2, _SCON, 5); //- SBIT( SM1, _SCON, 6); //- //SBIT( SM0, _SCON, 7); //- (8051) SBIT( SM0, _SCON, 7); /// Write (N76E003) SBIT( FE, _SCON, 7); /// Read
//SFR(SBUF, _SBUF); //- XXXX'XXXX Serial Port 0 Data Buffer (8051) SFR(SBUF, _SBUF); /// 0000'0000 Serial Port 0 Data Buffer (N76E003)
SFR(SBUF_1, _SBUF_1); /// 0000'0000 Serial port 1 data buffer
SFR(EIE, _EIE); /// 0000'0000 Extensive interrupt enable
SFR(EIE1, _EIE1); /// 0000'0000 Extensive interrupt enable 1
SFR(CHPCON, _CHPCON); /// TA 0000'00C0 Chip control
//SFR(P2, _P2); //- 1111'1111 Port 2 (8051) SFR(P2, _P2); /// 0000'000X Port 2 (N76E003) SBIT( P2_0, _P2, 0); //- SBIT( P20, _P2, 0); //= SBIT( RST, _P2, 0); /// //SBIT( P2_1, _P2, 1); //- Not available on N76E003 //SBIT( P2_2, _P2, 2); //- Not available on N76E003 //SBIT( P2_3, _P2, 3); //- Not available on N76E003 //SBIT( P2_4, _P2, 4); //- Not available on N76E003 //SBIT( P2_5, _P2, 5); //- Not available on N76E003 //SBIT( P2_6, _P2, 6); //- Not available on N76E003 //SBIT( P2_7, _P2, 7); //- Not available on N76E003
SFR(AUXR1, _AUXR1); /// 0000'0000 Auxiliary register 1
SFR(BODCON0, _BODCON0); /// TA CCCC'XC0X Brown-out detection control 0
SFR(IAPTRG, _IAPTRG); /// TA 0000'0000 IAP trigger
SFR(IAPUEN, _IAPUEN); /// TA 0000'0000 IAP update enable
SFR(IAPAL, _IAPAL); /// 0000'0000 IAP address low byte
SFR(IAPAH, _IAPAH); /// 0000'0000 IAP address high byte
//SFR(IE, _IE); //- 0XX0'0000 Interrupt Enable (8051) //SFR(IE, _IE); //+ 0X00'0000 Interrupt Enable (8052) SFR(IE, _IE); /// 0000'0000 Interrupt Enable (N76E003) SBIT(EX0, _IE, 0); //- SBIT(ET0, _IE, 1); //- SBIT(EX1, _IE, 2); //- SBIT(ET1, _IE, 3); //- SBIT(ES, _IE, 4); //- SBIT(EBOD, _IE, 5); /// (N76E003) //SBIT(ET2, _IE, 5); //- (8051) SBIT(EADC, _IE, 6); /// SBIT(EA, _IE, 7); //-
SFR(SADDR, _SADDR); /// 0000'0000 Slave 0 address
SFR(WDCON, _WDCON); /// TA 0000'0111 Watchdog timer control
SFR(BODCON1, _BODCON1); /// TA 0000'0001 Brown-out detection control 1
SFR(P3M1, _P3M1); /// 0000'0001 P3 mode select 1
SFR(P3S, _P3S); /// Page1 0000'0000 P3 Schmitt trigger input
SFR(P3M2, _P3M2); /// 0000'0000 P3 mode select 2
SFR(P3SR, _P3SR); /// Page1 0000'0000 P3 slew rate
SFR(IAPFD, _IAPFD); /// 0000'0000 IAP flash data
SFR(IAPCN, _IAPCN); /// 0011'0000 IAP control
//SFR(P3, _P3); //- 1111'1111 Port 3 (8051) SFR(P3, _P3); /// 0000'0001 Port 3 (N76E003) SBIT( P3_0, _P3, 0); //- SBIT( P30, _P3, 0); //= //SBIT( RXD, _P3, 0); //- Software defined on N76E003 SBIT( INT0, _P3, 0); /// SBIT( XIN, _P3, 0); /// //SBIT( P3_1, _P3, 1); //- Not available on N76E003 //SBIT( P31, _P3, 1); //= Not available on N76E003 //SBIT( TXD, _P3, 1); //- Software defined on N76E003 //SBIT( P3_2, _P3, 2); //= Not available on N76E003 //SBIT( P32, _P3, 2); //= Not available on N76E003 //SBIT( INT0, _P3, 2); //- Mapped to P3.0 on N76E003 //SBIT( P3_3, _P3, 3); //- Not available on N76E003 //SBIT( P33, _P3, 3); //- Not available on N76E003 //SBIT( INT1, _P3, 3); //- Mapped to P1.7 on N76E003 //SBIT( P3_4, _P3, 4); //- Not available on N76E003 //SBIT( P34, _P3, 4); //- Not available on N76E003 //SBIT( T0, _P3, 4); //- Mapped to P0.5 on N76E003 //SBIT( P3_5, _P3, 5); //- Not available on N76E003 //SBIT( P35, _P3, 5); //- Not available on N76E003 //SBIT( T1, _P3, 5); //- Mapped to P0.0 on N76E003 //SBIT( P3_6, _P3, 6); //- Not available on N76E003 //SBIT( P36, _P3, 6); //- Not available on N76E003 //SBIT( WR, _P3, 6); //- Not available on N76E003 //SBIT( P3_7, _P3, 7); //- Not available on N76E003 //SBIT( P37, _P3, 7); //- Not available on N76E003 //SBIT( RD, _P3, 7); //- Not available on N76E003
SFR(P0M1, _P0M1); /// 1111'1111 P0 mode select 1
SFR(P0S, _P0S); /// Page1 0000'0000 P0 Schmitt trigger input
SFR(P0M2, _P0M2); /// 0000'0000 P0 mode select 2
SFR(P0SR, _P0SR); /// Page1 0000'0000 P0 slew rate
SFR(P1M1, _P1M1); /// 1111'1111 P1 mode select 1
SFR(P1S, _P1S); /// Page1 0000'0000 P1 Schmitt trigger input
SFR(P1M2, _P1M2); /// 0000'0000 P1 mode select 2
SFR(P1SR, _P1SR); /// Page1 0000'0000 P1 slew rate
SFR(P2S, _P2S); /// 0000'0000 P20 setting and Timer 0/1 output enable
SFR(IPH, _IPH); /// 0000'0000 Interrupt priority high
SFR(PWMINTC, _PWMINTC); ///Page1 0000'0000 PWM interrupt control
//SFR(IP, _IP); //- XXX0'0000 Interrupt priority (8051) //SFR(IP, _IP); //+ XX00'0000 Interrupt priority (8052) SFR(IP, _IP); /// 0000'0000 Interrupt priority (N76E003) SBIT(PX0, _IP, 0); //- SBIT(PT0, _IP, 1); //- SBIT(PX1, _IP, 2); //- SBIT(PT1, _IP, 3); //- SBIT(PS, _IP, 4); //- SBIT(PBOD, _IP, 5); /// (N76E003) //SBIT(PT2, _IP, 5); //- (8051) SBIT(PADC, _IP, 6); ///
SFR(SADEN, _SADEN); /// 0000'0000 Slave 0 address mask
SFR(SADEN_1, _SADEN_1); /// 0000'0000 Slave 1 address mask
SFR(SADDR_1, _SADDR_1); /// 0000'0000 Slave 1 address
SFR(I2DAT, _I2DAT); /// 0000'0000 I2C data
SFR(I2STAT, _I2STAT); /// 1111'1000 I2C status
SFR(I2CLK, _I2CLK); /// 0000'1001 I2C clock
SFR(I2TOC, _I2TOC); /// 0000'0000 I2C time-out counter
SFR(I2CON, _I2CON); /// 0000'0000 I2C control SBIT( I2CPX, _I2CON, 0); /// SBIT( AA, _I2CON, 2); /// SBIT( SI, _I2CON, 3); /// SBIT( STO, _I2CON, 4); /// SBIT( STA, _I2CON, 5); /// SBIT( I2CEN, _I2CON, 6); ///
SFR(I2ADDR, _I2ADDR); /// 0000'0000 I2C own slave address
SFR(ADCRL, _ADCRL); /// 0000'0000 ADC result low byte
SFR(ADCRH, _ADCRH); /// 0000'0000 ADC result high byte
SFR(T3CON, _T3CON); /// 0000'0000 Timer 3 control
SFR(PWM4H, _PWM4H); /// Page1 0000'0000 PWM4 duty high byte
SFR(RL3, _RL3); ///
SFR(PWM5H, _PWM5H); /// Page1 0000'0000 PWM5 duty high byte
SFR(RH3, _RH3); /// 0000'0000 Timer 3 reload high byte
SFR(PIOCON1, _PIOCON1); /// Page1 0000'0000 PWM I/O switch 1
SFR(TA, _TA); /// 0000'0000 Timed access protection
SFR(T2CON, _T2CON); //+ 0000'0000 Timer/Counter 2 Control SBIT( CM_RL2, _T2CON, 0); //+ //SBIT( CP_RL2, _T2CON, 0); //+ (8051) //SBIT( C_T2, _T2CON, 1); //+ (8051) SBIT( TR2, _T2CON, 2); //+ //SBIT( EXEN2, _T2CON, 3); //+ (8051) //SBIT( TCLK, _T2CON, 4); //+ (8051) //SBIT( RCLK, _T2CON, 5); //+ (8051) //SBIT( EXF2, _T2CON, 6); //+ (8051) SBIT(TF2, _T2CON, 7); //+
SFR(T2MOD, _T2MOD); /// 0000'0000 Timer 2 mode
SFR(RCMP2L, _RCMP2L); /// 0000'0000 Timer 2 compare low byte (N76E003)
//#define _RCAP2L 0xCA //SFR(RCAP2L, _RCAP2L); //+ 0000'0000 T/C 2 Capture Reg. Low byte (8052)
SFR(RCMP2H, _RCMP2H); /// 0000'0000 Timer 2 compare high byte (N76E003)
//#define _RCAP2H 0xCB //SFR(RCAP2H, _RCAP2H); //+ 0000'0000 T/C 2 Capture Reg. High byte (8052)
SFR(TL2, _TL2); //+ 0000'0000 Timer/Counter 2 Low Byte
SFR(PWM4L, _PWM4L); /// Page1 0000'0000 PWM4 duty low byte
SFR(TH2, _TH2); //+ 0000'0000 Timer/Counter 2 High Byte
SFR(PWM5L, _PWM5L); ///Page1 0000'0000 PWM5 duty low byte
SFR(ADCMPL, _ADCMPL); /// 0000'0000 ADC compare low byte
SFR(ADCMPH, _ADCMPH); /// 0000'0000 ADC compare high byte
SFR(PSW, _PSW); //- SBIT( P, _PSW, 0); //- SBIT( F1, _PSW, 1); //- SBIT( OV, _PSW, 2); //- SBIT( RS0, _PSW, 3); //- SBIT( RS1, _PSW, 4); //- SBIT( F0, _PSW, 5); //- SBIT( AC, _PSW, 6); //- SBIT( CY, _PSW, 7); //-
SFR(PWMPH, _PWMPH); /// 0000'0000 PWM period high byte
SFR(PWM0H, _PWM0H); /// 0000'0000 PWM0 duty high byte
SFR(PWM1H, _PWM1H); /// 0000'0000 PWM1 duty high byte
SFR(PWM2H, _PWM2H); /// 0000'0000 PWM2 duty high byte
SFR(PWM3H, _PWM3H); /// 0000'0000 PWM3 duty high byte
SFR(PNP, _PNP); /// 0000'0000 PWM negative polarity
SFR(FBD, _FBD); /// 0000'0000 Brake data
SFR(PWMCON0, _PWMCON0); /// 0000'0000 PWM control 0 SBIT( CLRPWM, _PWMCON0, 4); /// SBIT( PWMF, _PWMCON0, 5); /// SBIT( LOAD, _PWMCON0, 6); /// SBIT( PWMRUN, _PWMCON0, 7); ///
SFR(PWMPL, _PWMPL); /// 0000'0000 PWM period low byte
SFR(PWM0L, _PWM0L); /// 0000'0000 PWM0 duty low byte
SFR(PWM1L, _PWM1L); /// 0000'0000 PWM1 duty low byte
SFR(PWM2L, _PWM2L); /// 0000'0000 PWM2 duty low byte
SFR(PWM3L, _PWM3L); /// 0000'0000 PWM3 duty low byte
SFR(PIOCON0, _PIOCON0); /// 0000'0000 PWM I/O switch 0
SFR(PWMCON1, _PWMCON1); /// 0000'0000 PWM control 1
SFR(ACC, _ACC); //- 0000'0000 Accumulator SBIT( ACC_0, _ACC, 0); //- SBIT( ACC_1, _ACC, 1); //- SBIT( ACC_2, _ACC, 2); //- SBIT( ACC_3, _ACC, 3); //- SBIT( ACC_4, _ACC, 4); //- SBIT( ACC_5, _ACC, 5); //- SBIT( ACC_6, _ACC, 6); //- SBIT( ACC_7, _ACC, 7); //-
SFR(ADCCON1, _ADCCON1); /// 0000'0000 ADC control 1
SFR(ADCCON2, _ADCCON2); /// 0000'0000 ADC control 2
SFR(ADCDLY, _ADCDLY); /// 0000'0000 ADC trigger delay
SFR(C0L, _C0L); /// 0000'0000 Input capture 0 low byte
SFR(C0H, _C0H); /// 0000'0000 Input capture 0 high byte
SFR(C1L, _C1L); /// 0000'0000 Input capture 1 low byte
SFR(C1H, _C1H); /// 0000'0000 Input capture 1 high byte
SFR(ADCCON0, _ADCCON0); /// 0000'0000 ADC control 0 SBIT( ADCHS0, _ADCCON0, 0); /// SBIT( ADCHS1, _ADCCON0, 1); /// SBIT( ADCHS2, _ADCCON0, 2); /// SBIT( ADCHS3, _ADCCON0, 3); /// SBIT( ETGSEL0, _ADCCON0, 4); /// SBIT( ETGSEL1, _ADCCON0, 5); /// SBIT( ADCS, _ADCCON0, 6); /// SBIT( ADCF, _ADCCON0, 7); ///
SFR(PICON, _PICON); /// 0000'0000 Pin interrupt control
SFR(PINEN, _PINEN); /// 0000'0000 Pin interrupt low level/falling edge enable
SFR(PIPEN, _PIPEN); /// 0000'0000 Pin interrupt high level/rising edge enable
SFR(PIF, _PIF); /// 0000'0000 Pin interrupt flag
SFR(C2L, _C2L); /// 0000'0000 Input capture 2 low byte
SFR(C2H, _C2H); /// 0000'0000 Input capture 2 high byte
SFR(EIP, _EIP); /// 0000'0000 Extensive interrupt priority
SFR(B, _B); //- 0000'0000 B register SBIT( B_0, _B, 0); //- SBIT( B_1, _B, 1); //- SBIT( B_2, _B, 2); //- SBIT( B_3, _B, 3); //- SBIT( B_4, _B, 4); //- SBIT( B_5, _B, 5); //- SBIT( B_6, _B, 6); //- SBIT( B_7, _B, 7); //-
SFR(CAPCON3, _CAPCON3); /// 0000'0000 Input capture control 3
SFR(CAPCON4, _CAPCON4); /// 0000'0000 Input capture control 4
SFR(SPCR, _SPCR); /// 0000'0000 SPI control
SFR(SPCR2, _SPCR2); ///Page1 0000'0000 SPI control 2
SFR(SPSR, _SPSR); /// 0000'0000 SPI status
SFR(SPDR, _SPDR); /// 0000'0000 SPI data
SFR(AINDIDS, _AINDIDS); /// 0000'0000 ADC channel digital input disable
SFR(EIPH, _EIPH); /// 0000'0000 Extensive interrupt priority high
SFR(SCON_1, _SCON_1); /// 0000'0000 Serial port 1 control SBIT( RI_1, _SCON_1, 0); /// SBIT( TI_1, _SCON_1, 1); /// SBIT( RB8_1, _SCON_1, 2); /// SBIT( TB8_1, _SCON_1, 3); /// SBIT( REN_1, _SCON_1, 4); /// SBIT( SM2_1, _SCON_1, 5); /// SBIT( SM1_1, _SCON_1, 6); /// SBIT( SM0_1, _SCON_1, 7); /// Write SBIT( FE_1, _SCON_1, 7); /// Read
SFR(PDTEN, _PDTEN); /// TA 0000'0000 PWM dead time enable
SFR(PDTCNT, _PDTCNT); /// TA 0000'0000 PWM dead-time counter
SFR(PMEN, _PMEN); /// 0000'0000 PWM mask enable
SFR(PMD, _PMD); /// 0000'0000 PWM mask data
SFR(PORDIS, _PORDIS); /// TA 0000'0000 POR disable
SFR(EIP1, _EIP1); /// 0000'0000 Extensive interrupt priority 1
SFR(EIPH1, _EIPH1); /// 0000'0000 Extensive interrupt priority high 1
//Reset vector absolute address declaration
//Interrupt numbers: Address = ( Number * 8 ) + 3
snovotill
commented
3 years ago And here is a blink demo main.c:
// Blink example for all mcs51 boards
/---------------------------------------------------------- SELECT BOARD ----------------------------------------------------------/ //Not needed for PlatformIO since the board definition file //automatically activates macros by which we can identify it, //like STM8S_NUCLEO_207K8 etc.
//#define n76e003 //#define stc15f104w //#define stc15w408as
/---------------------------------------------------------- INCLUDE FILES BY BOARD NAME IN ALPHABETICAL ORDER ----------------------------------------------------------/
//print this out as an info during compilation
//print this out as an info during compilation
//print this out as an info during compilation
//print this out as an info during compilation
//print this out as an info during compilation
//print this out as an info during compilation
//print this out as an info during compilation
//print this out as an info during compilation
/----------------------------------------------------------------------------- MAIN ROUTINE -----------------------------------------------------------------------------/ void main(void) { INIT_PIN // Macro if needed to initialize output pin while (1) { ledPin = 0x00; // LED on delay_c_ds(250); // Software delay 2500ms ledPin = 0xff; // LED off delay_s_ds(250); // Software delay 2500ms
// int n;
// ledPin = 0; // LED on
// for (n = 0; n < 50000; n++); // waste some cycles
// ledPin = 1; // LED off
// for (n = 0; n < 50000; n++); // waste some cycles
}} /----------------------------------------------------------------------------- END OF MODULE -----------------------------------------------------------------------------/
snovotill
commented
3 years ago And the associated delay.h:
void delay_c_ms(unsigned char ms); void delay_s_ms(unsigned char ms); void delay_c_ds(unsigned char ds); void delay_s_ds(unsigned char ds);
And finally the delay.c:
//#define MAIN_Fosc 11059200L //Define the clock
void delay_c_ms(unsigned char ms) //Software delay in mili-sec { //Calibrated for STC on SDCC unsigned int i; do { i = MAIN_Fosc / 13000; while (--i); // 14T per loop } while (--ms); }
void delay_c_ds(unsigned char ds) //Software delay in deci-sec { //Calibrated for STC on SDCC unsigned int i; do { i = MAIN_Fosc / 1300; while (--i); // 14T per loop } while (--ds); }
void delay_s_ms(unsigned char ms) //Software delay in mili-sec { //Calibrated for Nuvoton N76E003 ms; //Must declare delay variable asm MOV R2,dpl //Variable ms was passed via dpl 00001$: MOV R1,#0x08 //8 x 12.5ms produces 1ms total 00002$: MOV R0,#0xFA //FA is 12.5ms (or C7 is 100us) 00003$: DJNZ R0,00003$ DJNZ R1,00002$ DJNZ R2,00001$ endasm; }
void delay_s_ds(unsigned char ds) //Software delay in deci-sec { //Calibrated for Nuvoton N76E003 ds; //Must declare delay variable asm MOV R2,dpl //Variable ds was passed via dpl 00001$: MOV R1,#0x50 //80 x 12.5ms produces 1ds total 00002$: MOV R0,#0xFA //FA is 12.5ms (or C7 is 100us) 00003$: DJNZ R0,00003$ DJNZ R1,00002$ DJNZ R2,00001$ endasm; }
ivankravets
commented
2 years ago @snovotill thanks for the PR https://github.com/platformio/platform-intel_mcs51/pull/41
Hello, thanks for the great works. Could you kindly add support for the n76E003at20 chip from nuvoton. Thanks