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plctlab / plct-gem5

upstream: https://github.com/RALC88/gem5
BSD 3-Clause "New" or "Revised" License
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Related to vector lanes in Gem5 for RISC-V Vector #23

Open soniab opened 2 years ago

soniab commented 2 years ago

How many vector lanes does this Gem5 for RISC-V Vector support? Is it possible to change vector lanes at this point?

huxuan0307 commented 1 year ago

Our implementation uses register renaming instead of vector lanes. If you want to limit the number of vector execution units, you can modify the code of the O3CPU.

soniab commented 1 year ago

Thank you for clarifying this. I am using RISC-V MinorCPU, so it will be the same for in-order CPUs too. I have checked "BaseMinorCPU.py" and have observed that only one vector unit (MinorDefaultVecFU) is being used here. If I want to change the number of vector execution units then will it be enough to add the vector units here? Do I need to change some other files too?