This patch utilizes RISC-V 'V' extension to support '_vec' suffixed TCG ops in RISC-V backend. This is a very preliminary implementation, as it suffers from the following defects:
Multiple vset{i}vl{i} instruction will be emitted even when there's no vector instruction in between
v0 is reserved specifically for vector masking, and explicitly excluded from normal vector operation register allocations
Only the bare minimal set of TCG ops are implemented. There should be more ops that could be done.
This patch utilizes RISC-V 'V' extension to support '_vec' suffixed TCG ops in RISC-V backend. This is a very preliminary implementation, as it suffers from the following defects:
v0is reserved specifically for vector masking, and explicitly excluded from normal vector operation register allocations