This happens because the transfer error bit is high in the HISR/LISR DMA interrupt status register. The behaviour that is seen is that the tx dma appears to be "stuck" (the processor keeps running fine, but nothing comes out of the uart). Using the debugger, we see that even after setting the stream enable bit, the stream remains disabled. This is because the TE bit is still set (by hardware).
By enabling the TE interrupt and clearing the TE bit when that interrupt is fired, the DMA sends garbage from its buffer (good thing we will use a checksum for comms!) and then the uart tx resumes as expected. See 0b84c5d5d67cc32223884f22fa4aa0ae428f9c56.
Occasionally the tx dma stream gets stuck.
This happens because the transfer error bit is high in the
HISR/LISRDMA interrupt status register. The behaviour that is seen is that the tx dma appears to be "stuck" (the processor keeps running fine, but nothing comes out of the uart). Using the debugger, we see that even after setting the stream enable bit, the stream remains disabled. This is because the TE bit is still set (by hardware).By enabling the TE interrupt and clearing the TE bit when that interrupt is fired, the DMA sends garbage from its buffer (good thing we will use a checksum for comms!) and then the uart tx resumes as expected. See 0b84c5d5d67cc32223884f22fa4aa0ae428f9c56.
This needs to be done for the f3 chip as well.