PR#7074 consolidated SSE2 and AVX related optimization options into MPL's configure because only MPL explicitly use them. MPICH's CFLAGS no longer has those options. However, with Intel compilers, this does results in some performance degradation. Therefore, we need to propagate the CFLAGS in MPL back into the MPICH configure.
This PR creates a MPL_CFLAGS in the localdefs that allows the PAC_CONFIG_MPL macro to add it to the main CFLAGS.
This is an alternative and probably better solution than the 2nd commit in #7150 .
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Pull Request Description
PR#7074 consolidated SSE2 and AVX related optimization options into MPL's configure because only MPL explicitly use them. MPICH's CFLAGS no longer has those options. However, with Intel compilers, this does results in some performance degradation. Therefore, we need to propagate the CFLAGS in MPL back into the MPICH configure.
This PR creates a
MPL_CFLAGS
in the localdefs that allows the PAC_CONFIG_MPL macro to add it to the main CFLAGS.This is an alternative and probably better solution than the 2nd commit in #7150 .
Author Checklist
module: short description
Commit message explains what's in the commit.