pokemon-speedrunning / gambatte-speedrun

Fork of https://github.com/sinamas/gambatte with Pokemon speedrunning-related changes.
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MBC3+RAM+RTC invalid rambank/rtc switches are more complicated than thought #62

Closed CasualPokePlayer closed 3 years ago

CasualPokePlayer commented 4 years ago

I've talked about this on the PSR server, but essentially, there appears to be something within the MBC3 where if an invalid "bank switch" is sent to the chip, it will essentially lock itself and will not return any data (ie same behavior as locked SRAM). To be clear, I mean invalid combos physically sent to the chip, as all of bits 0-3 are connected to the MBC, with bits 2-3 exclusively connected to the RTC (they're connected to bits 0-1 too but that can also be shared with the rambanks). The normal mask bits 4-7 still applies as they are not connected to anything, it's just that bits 0-3 are all connected to the MBC and it does not like invalid combos being sent to it. Gambatte-Speedrun currently just masks bits 2-3 regardless and will just output data from an actual rambank, when this should not be the case.

Also, I don't believe this locking behavior should apply in the case of an MBC3 chip without RTC (as bits 2-3 would just not be connected to anything, like bits 4-7), although I don't have a way to test that so eh.