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polarfire-soc
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icicle-kit-reference-design
PolarFire SoC Icicle Kit Libero reference design
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Latest Icicle Release and using PCIE
#28
haroldnelson-2021
opened
1 week ago
2
Icicle TCL Script for 2024.09 Release has netlist errors in the FIC0 Peripherals SmartDesign
#27
haroldnelson-2021
closed
1 month ago
1
when I try to generate component in main file, suddenly close the libero and I can't generate component.
#26
msdarici
closed
1 month ago
0
Icicle TCL Script Update Needed
#25
haroldnelson-2021
opened
1 month ago
0
Offline execution of ICICLE reference kit TCL script
#24
karthyyy
opened
7 months ago
3
LSRAM corrupt RDATA in ModelSim, ref design generated using args: BFM_SIMULATION MSS_BAREMETAL
#23
Kian-KH
closed
1 year ago
5
Accessing the fabric memories
#22
cchalou98
opened
1 year ago
5
Error: Failure when executing Tcl script. [ Line 96: ERROR: Invalid parameter entry "MSS_MANUAL_DDR_PHY_OFFSET_ENABLE true"
#21
Kian-KH
closed
1 year ago
2
SoC Icicle Kit Reference Design Generation Tcl Script doesn't work with Libero® SoC v2022.3
#20
bekulio
closed
1 year ago
2
issue executing the script in Ubuntu
#18
controlpaths
closed
2 years ago
3
icicle-kit-reference-design-2022.08.zip build failed on Libero V2022.2
#17
zizimumu
closed
2 years ago
1
icicle-kit-reference-design-2022.08.zip build failed on Libero V2022.2
#16
zizimumu
closed
2 years ago
0
Building reference design on Libero
#14
Shivaraj199
closed
2 years ago
0
License information missing
#12
kowalski100
closed
1 year ago
2
AXI4 DMA controller DirectCore version 2.1.102 undefined modules
#9
mpsitech
closed
3 years ago
8
Cannot update "SoC-FPGA + zero-stage bootloader FlashPro Express programming file" with modern FlashPro Express software
#3
aleixrocks
closed
3 years ago
7
update eFP6 to rev B failed
#2
jinchenglee
closed
3 years ago
2