Getting errors from the example project "\\polarfire-soc-bare-metal-library\examples\mss-rtc\mpfs-rtc-time"

[henryding-emcore]

Hello,

I'm using this example project to do some FIC1 access where MSS is the master and the Fabric is the slave. The lines I added to u54_1.c are after "MSS_RTC_clear_irq()": uint64_t pointer2; pointer2 = 0x3000000000; pointer2 = 0x8877006605500000;

The following errors are what I got after I terminate the debug: Error: unable to halt hart 1 Error: dmcontrol=0x80010001 Error: dmstatus =0x00030c82

I'm able to see this writing happens on the fabric. But for some reason, the processor crashes with these errors.

[hughbreslin]

Hi @henryding-emcore sorry for the delay, unfortunately this repository has been deprecated, we are now using the bare-metal-examples repo.

In regards to this issue - have you taken the fabric out of reset? When you say you can see the writes on the fabric are they succeeding? Based on the address you've added some logic to the reference design on FIC1, if you've based your resets on the Icicle Kit Reference Design you will also have to set the fabric reset bit, it could be the case that the FIC itself is not in reset but the fabric peripherals are. The error you've copied is what occurs when a hart tries to access an illegal address or a peripheral in reset where the access doesn't return and the hart hangs waiting for it.

Please let me know if you're still facing this issue. You can enable the fabric using the following: SYSREG->SOFT_RESET_CR &= (uint32_t)~(SOFT_RESET_CR_FPGA_MASK);

[henryding-emcore]

Thanks, Hugh!

All the resets are released. It was fixed by adding a COREAXI4INTERCONNECTOR.

Thanks, Henry

From: hughbreslin @.> Sent: Thursday, April 28, 2022 7:41 AM To: polarfire-soc/polarfire-soc-bare-metal-library @.> Cc: Henry (Dahai) Ding (US) @.>; Mention @.> Subject: Re: [polarfire-soc/polarfire-soc-bare-metal-library] Getting errors from the example project "\polarfire-soc-bare-metal-library\examples\mss-rtc\mpfs-rtc-time" (Issue #20)

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Hi @henryding-emcorehttps://github.com/henryding-emcore sorry for the delay, unfortunately this repository has been deprecated, we are now using the bare-metal-exampleshttps://github.com/polarfire-soc/polarfire-soc-bare-metal-examples repo.

In regards to this issue - have you taken the fabric out of reset? When you say you can see the writes on the fabric are they succeeding? Based on the address you've added some logic to the reference design on FIC1, if you've based your resets on the Icicle Kit Reference Design you will also have to set the fabric reset bit, it could be the case that the FIC itself is not in reset but the fabric peripherals are. The error you've copied is what occurs when a hart tries to access an illegal address or a peripheral in reset where the access doesn't return and the hart hangs waiting for it.

Please let me know if you're still facing this issue. You can enable the fabric using the following: SYSREG->SOFT_RESET_CR &= (uint32_t)~(SOFT_RESET_CR_FPGA_MASK);

— Reply to this email directly, view it on GitHubhttps://github.com/polarfire-soc/polarfire-soc-bare-metal-library/issues/20#issuecomment-1112292389, or unsubscribehttps://github.com/notifications/unsubscribe-auth/AXRSIWVIJ5LZ5PFA4CYPWHLVHKPRBANCNFSM5QOF6BFQ. You are receiving this because you were mentioned.

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