pothosware / PothosZynq

DMA source and sink blocks for Xilinx Zynq FPGAs
https://github.com/pothosware/PothosZynq/wiki
Boost Software License 1.0
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FPGA logic to create tuser from stat/ctrl user data #3

Open guruofquality opened 9 years ago

guruofquality commented 9 years ago

We want to create a AXI DMA channel support "lite" that can deal with tuser without requiring the AXI DMA channel mode which requires additional resources and has S2MM limitations for automatic SG table advancement.

The control bus already forwards arbitrary user data from scatter gather entries and vice-versa for status bus. This can be used with a simple state machine to drive/read-in tuser.