povik / yosys-slang

SystemVerilog frontend for Yosys
ISC License
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Not knowing the width of a wire doesn't end up in an error #24

Closed alikates closed 3 months ago

alikates commented 3 months ago

I was writing a test for struct assigment and indexing when i stumbled upon this error:

yosys> read_slang tests/selects/assign_struct.sv 

1. Executing SLANG frontend.
ERROR: Assert `wire' failed in slang_frontend.cc:2492.

The relevant part of the test is this (notice WIDTH is undefined):

module t01(in0);
    input logic [WIDTH-1:0] in0;
endmodule

Looks like it doesn't notice that WIDTH is not defined, and instead of throwing an error it directly skips adding the wire to the netlist. Eventually the wire is looked up by ID and because it isn't found, the assertion fails.

povik commented 3 months ago

Yes, let me address this right away. It's due to the frontend trying to construct the netlist even if the underlying slang elaboration (inside driver.createCompilation();) raised errors. What we should do is error out early and let the user see the slang errors.

povik commented 3 months ago

This and similar crashes should be fixed with 90241a2:

-- Running command `read_slang assign_struct.sv' --

1. Executing SLANG frontend.
Top level design units:
    t01

assign_struct.sv:2:18: error: use of undeclared identifier 'WIDTH'
    input logic [WIDTH-1:0] in0;
                 ^~~~~

Build failed: 1 error, 0 warnings
ERROR: Compilation failed

Unfortunately we now have a hard dependency on a slang patch, let's see if it's taken up soon.