Allow bit selection on all bitstream-convertible signals

povik / yosys-slang

SystemVerilog frontend for Yosys

ISC License

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Allow bit selection on all bitstream-convertible signals #25

Closed alikates closed 3 months ago

alikates commented 3 months ago

This should allow bit and range indexing of packed structs and other similar signals.

Btw, when writing the test I noticed there seems to be an issue when lowering from assert with a struct member access to a $check cell: somehow the arguments get lost. I will open an issue on this.

povik commented 3 months ago

See 6fa347 for fix of the CI failure

alikates commented 3 months ago

Thanks!