Open phsauter opened 1 month ago
Explicit instantiations of standard cells like this:
module tc_clk_inverter ( input logic clk_i, output logic clk_o ); (* keep *)(* dont_touch = "true" *) sg13g2_inv_1 i_inv ( .A ( clk_i ), .Y ( clk_o ) );
Produce the following error:
target/ihp13/src/tc_clk.sv:14:3: error: unknown module 'sg13g2_inv_1' sg13g2_inv_1 i_inv (
Even if the standard cells have been loaded into Yosys using read_liberty.
read_liberty
My guess is that the previously loaded modules/cells are not communicated from Yosys to slang.
That's right. As a stopgap measure there's --ignore-unknown-modules, see also #3.
--ignore-unknown-modules
Explicit instantiations of standard cells like this:
Produce the following error:
Even if the standard cells have been loaded into Yosys using
read_liberty
.My guess is that the previously loaded modules/cells are not communicated from Yosys to slang.