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povik / yosys-slang

SystemVerilog frontend for Yosys
ISC License
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Memories with initialization fail parsing #62

Closed povik closed 1 week ago

povik commented 1 month ago

Minimal test case:

module top();
    reg [7:0] m[2];
    initial m[0] <= 0;
endmodule
povik commented 1 week ago

Fixed in 1e9c97e, follow-up issue #69