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povik / yosys-slang

SystemVerilog frontend for Yosys
ISC License
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Support ports w/o direct correspondence to a net/variable #67

Open povik opened 1 month ago

povik commented 1 month ago

Take the following input

module mymod (
    output .p1(r[3:0]),
    output .p2(r[7:4]));
logic [7:0] r;
endmodule

Ports p1, p2 are missing from the emitted netlist.

povik commented 1 week ago

Caught in a2c832f and raised an error for. This ticket is now to add support for this case instead of erroring out